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Patch Status 32694-wwwdocs_gcc14_Add_RISCV_changes-1 #1416

Closed github-actions[bot] closed 5 months ago

github-actions[bot] commented 6 months ago

Precommit CI Run information

Logs can be found in the associated Github Actions run: https://github.com/ewlu/gcc-precommit-ci/actions/runs/8628227873

Patch information

Applied patches: 1 -> 1 Associated series: https://patchwork.sourceware.org/project/gcc/list/?series=32694 Last patch applied: https://patchwork.sourceware.org/project/gcc/patch/20240410075759.994891-1-kito.cheng@sifive.com/ Patch id: 88280

Build Targets

Some targets are built as multilibs. If a build target ends with multilib, please refer to the table below to see all the targets within that multilib. Target name -march string
newlib-rv64gc-lp64d-multilib rv32gc-ilp32d, rv64gc-lp64d
newlib-rv64gcv-lp64d-multilib rv64gcv-lp64d
linux-rv64gcv-lp64d-multilib rv32gcv-ilp32d, rv64gcv-lp64d

Target Information

Target Shorthand -march string
Bitmanip gc_zba_zbb_zbc_zbs

Notes

Testsuite results use a more lenient allowlist to reduce error reporting with flakey tests. Please take a look at the current allowlist. Results come from a sum file comparator. Each patch is applied to a well known, non-broken baseline taken from our gcc postcommit framework (here) which runs the full gcc testsuite every 6 hours. If you have any questions or encounter any issues which may seem like false-positives, please contact us at patchworks-ci@rivosinc.com

github-actions[bot] commented 6 months ago

Lint Status

The following issues have been found with 32694-wwwdocs_gcc14_Add_RISCV_changes-1 using gcc's ./contrib/check_GNU_style.py. Please use your best judgement when resolving these issues. These are only warnings and do not need to be resolved in order to merge your patch. If any of these warnings seem like false-positives that could be guarded against please contact me: patchworks-ci@rivosinc.com.

=== ERROR type #1: dot, space, space, new sentence (3 error(s)) ===
htdocs/gcc-14/changes.html:751:48:      performance tuning of the loop vectorizer.█The default value is
htdocs/gcc-14/changes.html:784:55:      specify a fixed length for scalable vector types.█This option is
htdocs/gcc-14/changes.html:790:49:      the <code>-mtls-dialect=desc</code> option.█The default behavior can be

=== ERROR type #2: lines should not exceed 80 characters (1 error(s)) ===
htdocs/gcc-14/changes.html:892:80:      <li>XiangShan's Nanhu microarchitecture (<code>xiangshan-nanhu</code>).</li>

Additional information

github-actions[bot] commented 6 months ago

Apply Status

Target Status
Baseline hash: https://github.com/gcc-mirror/gcc/commit/18e94e04dae724c61cbc13ace85fa68f2deda900 Failed
Tip of tree hash: https://github.com/gcc-mirror/gcc/commit/4be1cc5f50578fafcdcbd09160235066d76a3f86 Failed

Command

> git am ../patches/*.patch --whitespace=fix -q --3way --empty=drop

Output

error: sha1 information is lacking or useless (htdocs/gcc-14/changes.html).
error: could not build fake ancestor
hint: Use 'git am --show-current-patch=diff' to see the failed patch
Patch failed at 0001 wwwdocs: gcc-14: Add RISC-V changes
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
---
 htdocs/gcc-14/changes.html | 155 ++++++++++++++++++++++++++++++++++++-
 1 file changed, 154 insertions(+), 1 deletion(-)

diff --git a/htdocs/gcc-14/changes.html b/htdocs/gcc-14/changes.html
index 2d8968cf..6cbb2e8f 100644
--- a/htdocs/gcc-14/changes.html
+++ b/htdocs/gcc-14/changes.html
@@ -739,7 +739,160 @@ __asm (".global __flmap_lock"  "\n\t"

 <!-- <h3 id="s390">S/390, System z, IBM z Systems</h3> -->

-<!-- <h3 id="riscv">RISC-V</h3> -->
+<h3 id="riscv">RISC-V</h3>
+<ul>
+  <li>The SLP and loop vectorizer is now enabled for RISC-V when the vector
+      extension is enabled, thanks to Ju-Zhe Zhong from
+      <a href='https://rivai-ic.com.cn/'>RiVAI</a>,
+      Pan Li from <a href='https://www.intel.com/'>Intel</a>, and Robin Dapp
+      from <a href='https://www.ventanamicro.com/'>Ventana Micro</a> for
+      contributing most of the implementation!</li>
+  <li>The <code>-mrvv-max-lmul=</code> option has been introduced for
+      performance tuning of the loop vectorizer. The default value is
+      <code>-mrvv-max-lmul=m1</code>, which limits the maximum LMUL to 1.
+      The <code>-mrvv-max-lmul=dynamic</code> setting can dynamically select
+      the maximum LMUL value based on register pressure.</li>
+  <li>Atomic code generation has been improved and is now in conformance with
+      the latest psABI specification, thanks to Patrick O'Neill from
+      <a href='https://www.rivosinc.com/'>Rivos</a>.</li>
+  <li>Support for the vector intrinsics as specified in
+      <a href='https://github.com/riscv-non-isa/rvv-intrinsic-doc/tree/v1.0.x'>
+      version 1.0 of the RISC-V vector intrinsic specification</a>.</li>
+  <li>Support for the experimental vector crypto intrinsics as specified in
+      <a href='https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/234'>
+      RISC-V vector intrinsic specification</a>, thanks to Feng Wang et al.
+      from <a href="https://eswincomputing.com/">ESWIN Computing</a></li>
+  <li>Support for the T-head vector intrinsics.</li>
+  <li>Support for the scalar bitmanip and scalar crypto  intrinsics, thanks to
+      Liao Shihua from <a href="https://plctlab.org/">PLCT</a>.</li>
+  <li>Support for the large code model via option <code>-mcmodel=large</code>,
+      thanks to Kuan-Lin Chen from
+      <a href="https://www.andestech.com/">Andes Technology</a>.</li>
+  <li>Support for the standard vector calling convention variant, thanks to
+      Lehua Ding from <a href='https://rivai-ic.com.cn/'>RiVAI</a>.</li>
+  <li>Supports the <code>target</code> attribute, which allows users to compile
+      a function with specific extensions.</li>
+  <li><code>-march=</code> option no longer requires the architecture string
+      to be in canonical order, with only a few constraints remaining: the
+      architecture string must start with <code>rv[32|64][i|g|e]</code>, and
+      must use an underscore as the separator after a multi-letter extension.
+  </li>
+  <li><code>-march=help</code> option has been introduced to dump all
+      supported extensions.</li>
+  <li>Added experimental support for the <code>-mrvv-vector-bits=zvl</code>
+      option and the <code>riscv_rvv_vector_bits</code> attribute, which
+      specify a fixed length for scalable vector types. This option is
+      optimized for specific vector core implementations; however, the code
+      generated with this option is NOT portable,
+      thanks to Pan Li from <a href="https://www.intel.com/">Intel</a>.
+  </li>
+  <li>Support for TLS descriptors has been introduced, which can be enabled by
+      the <code>-mtls-dialect=desc</code> option. The default behavior can be
+      configured with <code>--with-tls=[trad|desc]</code>.</li>
+  <li>Support for the TLS descriptors, this can be enabled by
+      <code>-mtls-dialect=desc</code> and the default behavior can be configure
+      by <code>--with-tls=[trad|desc], thanks to Tatsuyuki Ishi from
+      <a href="https://bluewhale.systems/">Blue Whale Systems</a></code>
+  </li>
+  <li>Support for the following standard extensions has been added:
+    <ul>
+      <li>Vector crypto extensions:
+   <ul>
+     <li>Zvbb</li>
+     <li>Zvkb</li>
+     <li>Zvbc</li>
+     <li>Zvkg</li>
+     <li>Zvkned</li>
+     <li>Zvkhna</li>
+     <li>Zvkhnb</li>
+     <li>Zvksed</li>
+     <li>Zvksh</li>
+     <li>Zvkn</li>
+     <li>Zvknc</li>
+     <li>Zvkng</li>
+     <li>Zvks</li>
+     <li>Zvksc</li>
+     <li>Zvksg</li>
+     <li>Zvkt</li>
+   </ul>
+      </li>
+      <li>Code size reduction extensions:
+   <ul>
+     <li>Zca</li>
+     <li>Zcb</li>
+     <li>Zce</li>
+     <li>Zcf</li>
+     <li>Zcd</li>
+     <li>Zcmp</li>
+     <li>Zcmt</li>
+   </ul>
+      </li>
+      <li>Zicond</li>
+      <li>Zfa</li>
+      <li>Ztso</li>
+      <li>Zvfbfmin</li>
+      <li>Zvfhmin</li>
+      <li>Zvfh</li>
+      <li>Za64rs</li>
+      <li>Za128rs</li>
+      <li>Ziccif</li>
+      <li>Ziccrse</li>
+      <li>Ziccamoa</li>
+      <li>Zicclsm</li>
+      <li>Zic64b</li>
+      <li>Smaia</li>
+      <li>Smepmp</li>
+      <li>Smstateen</li>
+      <li>Ssaia</li>
+      <li>Sscofpmf</li>
+      <li>Ssstateen</li>
+      <li>Sstc</li>
+      <li>Svinval</li>
+      <li>Svnapot</li>
+      <li>Svpbmt</li>
+    </ul>
+  </li>
+  <li>Support for the following vendor extensions has been added:
+    <ul>
+      <li>T-Head:
+   <ul>
+     <li>XTheadVector</li>
+   </ul>
+      </li>
+      <li>CORE-V:
+   <ul>
+     <li>XCVmac</li>
+     <li>XCValu</li>
+     <li>XCVelw</li>
+     <li>XCVsimd</li>
+     <li>XCVbi</li>
+   </ul>
+      </li>
+      <li>Ventana Micro:
+   <ul>
+     <li>XVentanaCondops</li>
+   </ul>
+      </li>
+    </ul>
+  </li>
+  <li>The following new CPUs are supported through the <code>-mcpu</code>
+      option (GCC identifiers in parentheses).
+    <ul>
+      <li>SiFive's X280 (<code>sifive-x280</code>).</li>
+      <li>SiFive's P450 (<code>sifive-p450</code>).</li>
+      <li>SiFive's P670 (<code>sifive-p670</code>).</li>
+    </ul>
+  </li>
+  <li>The following new CPUs are supported through the <code>-mtune</code>
+      option (GCC identifiers in parentheses).
+    <ul>
+      <li>Generic out-of-order core (<code>generic-ooo</code>).</li>
+      <li>SiFive's P400 series (<code>sifive-p400-series</code>).</li>
+      <li>SiFive's P600 series (<code>sifive-p600-series</code>).</li>
+      <li>XiangShan's Nanhu microarchitecture (<code>xiangshan-nanhu</code>).</li>
+    </ul>
+  </li>
+</ul>

 <!-- <h3 id="rx">RX</h3> -->

Additional information