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commented
1 month ago Lint Status
The following issues have been found with 33926-v513_Internalfn_Support_new_IFN_SATADD_for_unsigned_scalar_int-1 using gcc's ./contrib/check_GNU_style.py. Please use your best judgement when resolving these issues. These are only warnings and do not need to be resolved in order to merge your patch. If any of these warnings seem like false-positives that could be guarded against please contact me: patchworks-ci@rivosinc.com.
=== ERROR type #1: blocks of 8 spaces should be replaced with tabs (1 error(s)) ===
gcc/config/riscv/vector.md:4065:50: [(set (match_operand:V_VLSI 0 "register_operand"████████ "=vd, vd, vr, vr, vd, vd, vr, vr")
=== ERROR type #2: dot, space, space, end of comment (5 error(s)) ===
gcc/config/riscv/riscv.cc:11296:24: /* Step-1: sum = x + y */
gcc/config/riscv/riscv.cc:11318:25: /* Step-2: lt = sum < x */
gcc/config/riscv/riscv.cc:11321:21: /* Step-3: lt = -lt */
gcc/config/riscv/riscv.cc:11324:34: /* Step-4: xmode_dest = sum | lt */
gcc/config/riscv/riscv.cc:11327:30: /* Step-5: dest = xmode_dest */
=== ERROR type #3: lines should not exceed 80 characters (5 error(s)) ===
gcc/config/riscv/autovec.md:2628:80: riscv_vector::expand_vec_usadd (operands[0], operands[1], operands[2], <MODE>mode);
gcc/config/riscv/vector.md:4065:80: [(set (match_operand:V_VLSI 0 "register_operand" "=vd, vd, vr, vr, vd, vd, vr, vr")
gcc/config/riscv/vector.md:4076:80: (match_operand:V_VLSI 3 "<binop_rhs1_predicate>" " vr, vr, vr, vr, vr, vr, vr, vr")
gcc/config/riscv/vector.md:4077:80: (match_operand:V_VLSI 4 "<binop_rhs2_predicate>" "<binop_rhs2_constraint>"))
gcc/config/riscv/vector.md:4078:80: (match_operand:V_VLSI 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0, vu, 0")))]
Precommit CI Run information
Logs can be found in the associated Github Actions run: https://github.com/ewlu/gcc-precommit-ci/actions/runs/9089011924
Patch information
Applied patches: 1 -> 1 Associated series: https://patchwork.sourceware.org/project/gcc/list/?series=33926 Last patch applied: https://patchwork.sourceware.org/project/gcc/patch/20240515021407.1287623-3-pan2.li@intel.com/ Patch id: 90152
Build Targets
multilib, please refer to the table below to see all the targets within that multilib.-marchstringrv32gc-ilp32d,rv64gc-lp64drv64gcv-lp64drv32gcv-ilp32d,rv64gcv-lp64dTarget Information
-marchstringgc_zba_zbb_zbc_zbsNotes
Testsuite results use a more lenient allowlist to reduce error reporting with flakey tests. Please take a look at the current allowlist. Results come from a sum file comparator. Each patch is applied to a well known, non-broken baseline taken from our gcc postcommit framework (here) which runs the full gcc testsuite every 6 hours. If you have any questions or encounter any issues which may seem like false-positives, please contact us at patchworks-ci@rivosinc.com