Patch Status 34059-RISCV_Split_vwaddwx_and_vwsubwx_and_add_helpers-1

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Precommit CI Run information

Logs can be found in the associated Github Actions run: https://github.com/ewlu/gcc-precommit-ci/actions/runs/9130778601

Patch information

Applied patches: 1 -> 1 Associated series: https://patchwork.sourceware.org/project/gcc/list/?series=34059 Last patch applied: https://patchwork.sourceware.org/project/gcc/patch/99adaa97-97e5-4ddb-bc56-af0d19088278@gmail.com/ Patch id: 90385

Build Targets

Some targets are built as multilibs. If a build target ends with multilib, please refer to the table below to see all the targets within that multilib.	Target name	-march string
newlib-rv64gc-lp64d-multilib	rv32gc-ilp32d, rv64gc-lp64d
newlib-rv64gcv-lp64d-multilib	rv64gcv-lp64d
linux-rv64gcv-lp64d-multilib	rv32gcv-ilp32d, rv64gcv-lp64d

Target Information

Target Shorthand	-march string
Bitmanip	gc_zba_zbb_zbc_zbs

Notes

Testsuite results use a more lenient allowlist to reduce error reporting with flakey tests. Please take a look at the current allowlist. Results come from a sum file comparator. Each patch is applied to a well known, non-broken baseline taken from our gcc postcommit framework (here) which runs the full gcc testsuite every 6 hours. If you have any questions or encounter any issues which may seem like false-positives, please contact us at patchworks-ci@rivosinc.com

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Lint Status

The following issues have been found with 34059-RISCV_Split_vwaddwx_and_vwsubwx_and_add_helpers-1 using gcc's ./contrib/check_GNU_style.py. Please use your best judgement when resolving these issues. These are only warnings and do not need to be resolved in order to merge your patch. If any of these warnings seem like false-positives that could be guarded against please contact me: patchworks-ci@rivosinc.com.

=== ERROR type #1: blocks of 8 spaces should be replaced with tabs (21 error(s)) ===
gcc/config/riscv/vector.md:3903:50:  [(set (match_operand:VWEXTI 0 "register_operand"████████████████ "=vd,vd, vr, vr")
gcc/config/riscv/vector.md:3907:46:      (match_operand 5 "vector_length_operand"████████      " rK,rK, rK, rK")
gcc/config/riscv/vector.md:3908:42:      (match_operand 6 "const_int_operand"████████████████  "  i, i,  i,  i")
gcc/config/riscv/vector.md:3909:42:      (match_operand 7 "const_int_operand"████████████████  "  i, i,  i,  i")
gcc/config/riscv/vector.md:3910:42:      (match_operand 8 "const_int_operand"████████████████  "  i, i,  i,  i")
gcc/config/riscv/vector.md:3914:47:     (match_operand:VWEXTI 3 "register_operand"████████     " vr,vr, vr, vr")
gcc/config/riscv/vector.md:3918:49:   (match_operand:VWEXTI 2 "vector_merge_operand"████████   " vu, 0, vu,  0")))]
gcc/config/riscv/vector.md:3925:50:  [(set (match_operand:VWEXTI 0 "register_operand"████████████████ "=vd,vd, vr, vr")
gcc/config/riscv/vector.md:3929:46:      (match_operand 5 "vector_length_operand"████████      " rK,rK, rK, rK")
gcc/config/riscv/vector.md:3930:42:      (match_operand 6 "const_int_operand"████████████████  "  i, i,  i,  i")
gcc/config/riscv/vector.md:3931:42:      (match_operand 7 "const_int_operand"████████████████  "  i, i,  i,  i")
gcc/config/riscv/vector.md:3932:42:      (match_operand 8 "const_int_operand"████████████████  "  i, i,  i,  i")
gcc/config/riscv/vector.md:3939:47:     (match_operand:VWEXTI 3 "register_operand"████████     " vr,vr, vr, vr"))
gcc/config/riscv/vector.md:3940:49:   (match_operand:VWEXTI 2 "vector_merge_operand"████████   " vu, 0, vu,  0")))]
gcc/config/riscv/vector.md:3947:50:  [(set (match_operand:VWEXTI 0 "register_operand"████████████████ "=vd,vd, vr, vr")
gcc/config/riscv/vector.md:3951:46:      (match_operand 5 "vector_length_operand"████████      " rK,rK, rK, rK")
gcc/config/riscv/vector.md:3952:42:      (match_operand 6 "const_int_operand"████████████████  "  i, i,  i,  i")
gcc/config/riscv/vector.md:3953:42:      (match_operand 7 "const_int_operand"████████████████  "  i, i,  i,  i")
gcc/config/riscv/vector.md:3954:42:      (match_operand 8 "const_int_operand"████████████████  "  i, i,  i,  i")
gcc/config/riscv/vector.md:3958:47:     (match_operand:VWEXTI 3 "register_operand"████████     " vr,vr, vr, vr")
gcc/config/riscv/vector.md:3962:49:   (match_operand:VWEXTI 2 "vector_merge_operand"████████   " vu, 0, vu,  0")))]

=== ERROR type #2: lines should not exceed 80 characters (27 error(s)) ===
gcc/config/riscv/vector.md:3903:80:  [(set (match_operand:VWEXTI 0 "register_operand"                 "=vd,vd, vr, vr")
gcc/config/riscv/vector.md:3906:80:            [(match_operand:<VM> 1 "vector_mask_operand"           " vm,vm,Wc1,Wc1")
gcc/config/riscv/vector.md:3907:80:             (match_operand 5 "vector_length_operand"              " rK,rK, rK, rK")
gcc/config/riscv/vector.md:3908:80:             (match_operand 6 "const_int_operand"                  "  i, i,  i,  i")
gcc/config/riscv/vector.md:3909:80:             (match_operand 7 "const_int_operand"                  "  i, i,  i,  i")
gcc/config/riscv/vector.md:3910:80:             (match_operand 8 "const_int_operand"                  "  i, i,  i,  i")
gcc/config/riscv/vector.md:3914:80:            (match_operand:VWEXTI 3 "register_operand"             " vr,vr, vr, vr")
gcc/config/riscv/vector.md:3917:80:                (match_operand:<VSUBEL> 4 "reg_or_0_operand"       " rJ,rJ, rJ, rJ"))))
gcc/config/riscv/vector.md:3918:80:          (match_operand:VWEXTI 2 "vector_merge_operand"           " vu, 0, vu,  0")))]
gcc/config/riscv/vector.md:3925:80:  [(set (match_operand:VWEXTI 0 "register_operand"                 "=vd,vd, vr, vr")
gcc/config/riscv/vector.md:3928:80:            [(match_operand:<VM> 1 "vector_mask_operand"           " vm,vm,Wc1,Wc1")
gcc/config/riscv/vector.md:3929:80:             (match_operand 5 "vector_length_operand"              " rK,rK, rK, rK")
gcc/config/riscv/vector.md:3930:80:             (match_operand 6 "const_int_operand"                  "  i, i,  i,  i")
gcc/config/riscv/vector.md:3931:80:             (match_operand 7 "const_int_operand"                  "  i, i,  i,  i")
gcc/config/riscv/vector.md:3932:80:             (match_operand 8 "const_int_operand"                  "  i, i,  i,  i")
gcc/config/riscv/vector.md:3938:80:                (match_operand:<VSUBEL> 4 "reg_or_0_operand"       " rJ,rJ, rJ, rJ")))
gcc/config/riscv/vector.md:3939:80:            (match_operand:VWEXTI 3 "register_operand"             " vr,vr, vr, vr"))
gcc/config/riscv/vector.md:3940:80:          (match_operand:VWEXTI 2 "vector_merge_operand"           " vu, 0, vu,  0")))]
gcc/config/riscv/vector.md:3947:80:  [(set (match_operand:VWEXTI 0 "register_operand"                 "=vd,vd, vr, vr")
gcc/config/riscv/vector.md:3950:80:            [(match_operand:<VM> 1 "vector_mask_operand"           " vm,vm,Wc1,Wc1")
gcc/config/riscv/vector.md:3951:80:             (match_operand 5 "vector_length_operand"              " rK,rK, rK, rK")
gcc/config/riscv/vector.md:3952:80:             (match_operand 6 "const_int_operand"                  "  i, i,  i,  i")
gcc/config/riscv/vector.md:3953:80:             (match_operand 7 "const_int_operand"                  "  i, i,  i,  i")
gcc/config/riscv/vector.md:3954:80:             (match_operand 8 "const_int_operand"                  "  i, i,  i,  i")
gcc/config/riscv/vector.md:3958:80:            (match_operand:VWEXTI 3 "register_operand"             " vr,vr, vr, vr")
gcc/config/riscv/vector.md:3961:80:                (match_operand:<VSUBEL> 4 "reg_or_0_operand"       " rJ,rJ, rJ, rJ"))))
gcc/config/riscv/vector.md:3962:80:          (match_operand:VWEXTI 2 "vector_merge_operand"           " vu, 0, vu,  0")))]

Additional information

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Apply Status

Target	Status
Baseline hash: https://github.com/gcc-mirror/gcc/commit/d477d683d5c6db90c80d348c795709ae6444ba7a	Failed
Tip of tree hash: https://github.com/gcc-mirror/gcc/commit/b59de4113262f2bee14147eb17eb3592f03d9556	Failed

Command

> git am ../patches/*.patch --whitespace=fix -q --3way --empty=drop

Output

error: sha1 information is lacking or useless (gcc/config/riscv/vector.md).
error: could not build fake ancestor
hint: Use 'git am --show-current-patch=diff' to see the failed patch
hint: When you have resolved this problem, run "git am --continue".
hint: If you prefer to skip this patch, run "git am --skip" instead.
hint: To restore the original branch and stop patching, run "git am --abort".
hint: Disable this message with "git config advice.mergeConflict false"
Patch failed at 0001 RISC-V: Split vwadd.wx and vwsub.wx and add helpers.
---
 gcc/config/riscv/vector.md                    | 62 ++++++++++++++++---
 .../gcc.target/riscv/rvv/base/pr115068-run.c  | 24 +------
 .../gcc.target/riscv/rvv/base/pr115068.c      | 26 ++++++++
 .../gcc.target/riscv/rvv/base/vwaddsub-1.c    | 47 ++++++++++++++
 4 files changed, 127 insertions(+), 32 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddsub-1.c

diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 107914afa3a..248461302dd 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -3900,27 +3900,71 @@ (define_insn "@pred_single_widen_add<any_extend:su><mode>"
    (set_attr "mode" "<V_DOUBLE_TRUNC>")])

 (define_insn "@pred_single_widen_<plus_minus:optab><any_extend:su><mode>_scalar"
-  [(set (match_operand:VWEXTI 0 "register_operand"                   "=vr,   vr")
+  [(set (match_operand:VWEXTI 0 "register_operand"                 "=vd,vd, vr, vr")
    (if_then_else:VWEXTI
      (unspec:<VM>
-       [(match_operand:<VM> 1 "vector_mask_operand"           "vmWc1,vmWc1")
-        (match_operand 5 "vector_length_operand"              "   rK,   rK")
-        (match_operand 6 "const_int_operand"                  "    i,    i")
-        (match_operand 7 "const_int_operand"                  "    i,    i")
-        (match_operand 8 "const_int_operand"                  "    i,    i")
+       [(match_operand:<VM> 1 "vector_mask_operand"       " vm,vm,Wc1,Wc1")
+        (match_operand 5 "vector_length_operand"              " rK,rK, rK, rK")
+        (match_operand 6 "const_int_operand"                  "  i, i,  i,  i")
+        (match_operand 7 "const_int_operand"                  "  i, i,  i,  i")
+        (match_operand 8 "const_int_operand"                  "  i, i,  i,  i")
         (reg:SI VL_REGNUM)
         (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
      (plus_minus:VWEXTI
-       (match_operand:VWEXTI 3 "register_operand"             "   vr,   vr")
+       (match_operand:VWEXTI 3 "register_operand"             " vr,vr, vr, vr")
        (any_extend:VWEXTI
          (vec_duplicate:<V_DOUBLE_TRUNC>
-       (match_operand:<VSUBEL> 4 "reg_or_0_operand"       "   rJ,   rJ"))))
-     (match_operand:VWEXTI 2 "vector_merge_operand"           "   vu,    0")))]
+       (match_operand:<VSUBEL> 4 "reg_or_0_operand"       " rJ,rJ, rJ, rJ"))))
+     (match_operand:VWEXTI 2 "vector_merge_operand"           " vu, 0, vu,  0")))]
   "TARGET_VECTOR"
   "vw<plus_minus:insn><any_extend:u>.wx\t%0,%3,%z4%p1"
   [(set_attr "type" "vi<widen_binop_insn_type>")
    (set_attr "mode" "<V_DOUBLE_TRUNC>")])

+(define_insn "@pred_single_widen_add<any_extend:su><mode>_extended_scalar"
+  [(set (match_operand:VWEXTI 0 "register_operand"                 "=vd,vd, vr, vr")
+   (if_then_else:VWEXTI
+     (unspec:<VM>
+       [(match_operand:<VM> 1 "vector_mask_operand"       " vm,vm,Wc1,Wc1")
+        (match_operand 5 "vector_length_operand"              " rK,rK, rK, rK")
+        (match_operand 6 "const_int_operand"                  "  i, i,  i,  i")
+        (match_operand 7 "const_int_operand"                  "  i, i,  i,  i")
+        (match_operand 8 "const_int_operand"                  "  i, i,  i,  i")
+        (reg:SI VL_REGNUM)
+        (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+     (plus:VWEXTI
+       (vec_duplicate:VWEXTI
+         (any_extend:<VEL>
+       (match_operand:<VSUBEL> 4 "reg_or_0_operand"       " rJ,rJ, rJ, rJ")))
+       (match_operand:VWEXTI 3 "register_operand"             " vr,vr, vr, vr"))
+     (match_operand:VWEXTI 2 "vector_merge_operand"           " vu, 0, vu,  0")))]
+  "TARGET_VECTOR"
+  "vwadd<any_extend:u>.wx\t%0,%3,%z4%p1"
+  [(set_attr "type" "viwalu")
+   (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+
+(define_insn "@pred_single_widen_sub<any_extend:su><mode>_extended_scalar"
+  [(set (match_operand:VWEXTI 0 "register_operand"                 "=vd,vd, vr, vr")
+   (if_then_else:VWEXTI
+     (unspec:<VM>
+       [(match_operand:<VM> 1 "vector_mask_operand"       " vm,vm,Wc1,Wc1")
+        (match_operand 5 "vector_length_operand"              " rK,rK, rK, rK")
+        (match_operand 6 "const_int_operand"                  "  i, i,  i,  i")
+        (match_operand 7 "const_int_operand"                  "  i, i,  i,  i")
+        (match_operand 8 "const_int_operand"                  "  i, i,  i,  i")
+        (reg:SI VL_REGNUM)
+        (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+     (minus:VWEXTI
+       (match_operand:VWEXTI 3 "register_operand"             " vr,vr, vr, vr")
+       (vec_duplicate:VWEXTI
+         (any_extend:<VEL>
+       (match_operand:<VSUBEL> 4 "reg_or_0_operand"       " rJ,rJ, rJ, rJ"))))
+     (match_operand:VWEXTI 2 "vector_merge_operand"           " vu, 0, vu,  0")))]
+  "TARGET_VECTOR"
+  "vwsub<any_extend:u>.wx\t%0,%3,%z4%p1"
+  [(set_attr "type" "viwalu")
+   (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+
 (define_insn "@pred_widen_mulsu<mode>"
   [(set (match_operand:VWEXTI 0 "register_operand"                  "=&vr,&vr")
    (if_then_else:VWEXTI
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr115068-run.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr115068-run.c
index 95ec8e06021..d552eb568f6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr115068-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr115068-run.c
@@ -3,26 +3,4 @@
 /* { dg-add-options riscv_v } */
 /* { dg-additional-options "-std=gnu99" } */

-#include <stdint.h>
-#include <riscv_vector.h>
-
-vfloat64m8_t
-test_vfwadd_wf_f64m8_m (vbool8_t vm, vfloat64m8_t vs2, float rs1, size_t vl)
-{
-  return __riscv_vfwadd_wf_f64m8_m (vm, vs2, rs1, vl);
-}
-
-char global_memory[1024];
-void *fake_memory = (void *) global_memory;
-
-int
-main ()
-{
-  asm volatile ("fence" ::: "memory");
-  vfloat64m8_t vfwadd_wf_f64m8_m_vd = test_vfwadd_wf_f64m8_m (
-    __riscv_vreinterpret_v_i8m1_b8 (__riscv_vundefined_i8m1 ()),
-    __riscv_vundefined_f64m8 (), 1.0, __riscv_vsetvlmax_e64m8 ());
-  asm volatile ("" ::"vr"(vfwadd_wf_f64m8_m_vd) : "memory");
-
-  return 0;
-}
+#include "pr115068.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr115068.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr115068.c
index 6d680037aa1..8359e81629d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr115068.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr115068.c
@@ -11,6 +11,18 @@ test_vfwadd_wf_f64m8_m (vbool8_t vm, vfloat64m8_t vs2, float rs1, size_t vl)
   return __riscv_vfwadd_wf_f64m8_m (vm, vs2, rs1, vl);
 }

+vint64m8_t
+test_vwadd_wx_i64m8_m (vbool8_t vm, vint64m8_t vs2, int32_t rs1, size_t vl)
+{
+  return __riscv_vwadd_wx_i64m8_m (vm, vs2, rs1, vl);
+}
+
+vint64m8_t
+test_vwsub_wx_i64m8_m (vbool8_t vm, vint64m8_t vs2, int32_t rs1, size_t vl)
+{
+  return __riscv_vwsub_wx_i64m8_m (vm, vs2, rs1, vl);
+}
+
 char global_memory[1024];
 void *fake_memory = (void *) global_memory;

@@ -23,7 +35,21 @@ main ()
     __riscv_vundefined_f64m8 (), 1.0, __riscv_vsetvlmax_e64m8 ());
   asm volatile ("" ::"vr"(vfwadd_wf_f64m8_m_vd) : "memory");

+  asm volatile ("fence" ::: "memory");
+  vint64m8_t vwadd_wx_i64m8_m_vd = test_vwadd_wx_i64m8_m (
+    __riscv_vreinterpret_v_i8m1_b8 (__riscv_vundefined_i8m1 ()),
+    __riscv_vundefined_i64m8 (), 1.0, __riscv_vsetvlmax_e64m8 ());
+  asm volatile ("" ::"vr"(vwadd_wx_i64m8_m_vd) : "memory");
+
+  asm volatile ("fence" ::: "memory");
+  vint64m8_t vwsub_wx_i64m8_m_vd = test_vwsub_wx_i64m8_m (
+    __riscv_vreinterpret_v_i8m1_b8 (__riscv_vundefined_i8m1 ()),
+    __riscv_vundefined_i64m8 (), 1.0, __riscv_vsetvlmax_e64m8 ());
+  asm volatile ("" ::"vr"(vwsub_wx_i64m8_m_vd) : "memory");
+
   return 0;
 }

 /* { dg-final { scan-assembler-not "vfwadd.wf\tv0.*v0" } } */
+/* { dg-final { scan-assembler-not "vwadd.wx\tv0.*v0" } } */
+/* { dg-final { scan-assembler-not "vwsub.wx\tv0.*v0" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddsub-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddsub-1.c
new file mode 100644
index 00000000000..1ee45823b48
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddsub-1.c
@@ -0,0 +1,47 @@
+/* { dg-do compile } */
+/* { dg-add-options riscv_v } */
+/* { dg-additional-options "-std=gnu99 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include <stdint.h>
+#include <riscv_vector.h>
+
+extern int8_t bla;
+
+/*
+** vwadd_wx_i64m8_m:
+**    vsetvli\s+zero,[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]
+**    vwadd\.wx\tv8,v8,a0,v0.t
+**    ret
+*/
+vint64m8_t
+vwadd_wx_i64m8_m (vbool8_t vm, vint64m8_t vs2, int64_t rs1, size_t vl)
+{
+  return __riscv_vwadd_wx_i64m8_m (vm, vs2, rs1, vl);
+}
+
+/*
+** vwsub_wx_i64m8_m:
+**    vsetvli\s+zero,[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]
+**    vwsub\.wx\tv8,v8,a0,v0.t
+**    ret
+*/
+vint64m8_t
+vwsub_wx_i64m8_m (vbool8_t vm, vint64m8_t vs2, int64_t rs1, size_t vl)
+{
+  return __riscv_vwsub_wx_i64m8_m (vm, vs2, rs1, vl);
+}
+
+/*
+** vwsub_wx_i32m8_m:
+**    vsetvli\s+zero,[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]
+**    ..
+**    vwadd\.wx\tv8,v8,a5,v0.t
+**    ret
+*/
+vint32m8_t
+vwadd_wx_i32m8_m (vbool4_t vm, vint32m8_t vs2, int16_t rs1, size_t vl)
+{
+  return __riscv_vwadd_wx_i32m8_m (vm, vs2, bla, vl);
+}
+
+/* { dg-final { check-function-bodies "**" "" } } */

Additional information