Patch Status 34686-RISCV_Add_basic_Zaamo_and_Zalrsc_support-2

[github-actions[bot]]

Precommit CI Run information

Logs can be found in the associated Github Actions run: https://github.com/ewlu/gcc-precommit-ci/actions/runs/9358047478

Patch information

Applied patches: 1 -> 2 Associated series: https://patchwork.sourceware.org/project/gcc/list/?series=34686 Last patch applied: https://patchwork.sourceware.org/project/gcc/patch/20240603215329.2664893-3-patrick@rivosinc.com/ Patch id: 91452

Build Targets

Some targets are built as multilibs. If a build target ends with multilib, please refer to the table below to see all the targets within that multilib.	Target name	-march string
newlib-rv64gc-lp64d-multilib	rv32gc-ilp32d, rv64gc-lp64d
newlib-rv64gcv-lp64d-multilib	rv64gcv-lp64d
linux-rv64gcv-lp64d-multilib	rv32gcv-ilp32d, rv64gcv-lp64d

Target Information

Target Shorthand	-march string
Bitmanip	gc_zba_zbb_zbc_zbs

Notes

Testsuite results use a more lenient allowlist to reduce error reporting with flakey tests. Please take a look at the current allowlist. Results come from a sum file comparator. Each patch is applied to a well known, non-broken baseline taken from our gcc postcommit framework (here) which runs the full gcc testsuite every 6 hours. If you have any questions or encounter any issues which may seem like false-positives, please contact us at patchworks-ci@rivosinc.com

[github-actions[bot]]

Lint Status

The following issues have been found with 34686-RISCV_Add_basic_Zaamo_and_Zalrsc_support-2 using gcc's ./contrib/check_GNU_style.py. Please use your best judgement when resolving these issues. These are only warnings and do not need to be resolved in order to merge your patch. If any of these warnings seem like false-positives that could be guarded against please contact me: patchworks-ci@rivosinc.com.

=== ERROR type #1: there should be exactly one space between function name and parenthesis (3 error(s)) ===
gcc/config/riscv/riscv.opt:251:4:Mask(ZAWRS)  Var(riscv_za_subext)
gcc/config/riscv/riscv.opt:253:4:Mask(ZAAMO)  Var(riscv_za_subext)
gcc/config/riscv/riscv.opt:255:4:Mask(ZALRSC) Var(riscv_za_subext)

Additional information

[github-actions[bot]]

Apply Status

Target	Status
Baseline hash: https://github.com/gcc-mirror/gcc/commit/16fb3abf0fb4b88ee0e27732db217909fa429a81	Failed
Tip of tree hash: https://github.com/gcc-mirror/gcc/commit/4cf2de9b5268224816a3d53fdd2c3d799ebfd9c8	Failed

Command

> git am ../patches/*.patch --whitespace=fix -q --3way --empty=drop

Output

error: patch failed: gcc/testsuite/lib/target-supports.exp:28
error: gcc/testsuite/lib/target-supports.exp: patch does not apply
error: Did you hand edit your patch?
It does not apply to blobs recorded in its index.
hint: Use 'git am --show-current-patch=diff' to see the failed patch
hint: When you have resolved this problem, run "git am --continue".
hint: If you prefer to skip this patch, run "git am --skip" instead.
hint: To restore the original branch and stop patching, run "git am --abort".
hint: Disable this message with "git config advice.mergeConflict false"
Patch failed at 0002 RISC-V: Add Zalrsc and Zaamo testsuite support
---
 .../riscv/amo-table-a-6-amo-add-1.c           |   2 +-
 .../riscv/amo-table-a-6-amo-add-2.c           |   2 +-
 .../riscv/amo-table-a-6-amo-add-3.c           |   2 +-
 .../riscv/amo-table-a-6-amo-add-4.c           |   2 +-
 .../riscv/amo-table-a-6-amo-add-5.c           |   2 +-
 .../riscv/amo-table-a-6-compare-exchange-1.c  |   2 +-
 .../riscv/amo-table-a-6-compare-exchange-2.c  |   2 +-
 .../riscv/amo-table-a-6-compare-exchange-3.c  |   2 +-
 .../riscv/amo-table-a-6-compare-exchange-4.c  |   2 +-
 .../riscv/amo-table-a-6-compare-exchange-5.c  |   2 +-
 .../riscv/amo-table-a-6-compare-exchange-6.c  |   2 +-
 .../riscv/amo-table-a-6-compare-exchange-7.c  |   2 +-
 .../riscv/amo-table-a-6-subword-amo-add-1.c   |   2 +-
 .../riscv/amo-table-a-6-subword-amo-add-2.c   |   2 +-
 .../riscv/amo-table-a-6-subword-amo-add-3.c   |   2 +-
 .../riscv/amo-table-a-6-subword-amo-add-4.c   |   2 +-
 .../riscv/amo-table-a-6-subword-amo-add-5.c   |   2 +-
 .../riscv/amo-table-ztso-amo-add-1.c          |   1 +
 .../riscv/amo-table-ztso-amo-add-2.c          |   1 +
 .../riscv/amo-table-ztso-amo-add-3.c          |   1 +
 .../riscv/amo-table-ztso-amo-add-4.c          |   1 +
 .../riscv/amo-table-ztso-amo-add-5.c          |   1 +
 .../riscv/amo-table-ztso-compare-exchange-1.c |   1 +
 .../riscv/amo-table-ztso-compare-exchange-2.c |   1 +
 .../riscv/amo-table-ztso-compare-exchange-3.c |   1 +
 .../riscv/amo-table-ztso-compare-exchange-4.c |   1 +
 .../riscv/amo-table-ztso-compare-exchange-5.c |   1 +
 .../riscv/amo-table-ztso-compare-exchange-6.c |   1 +
 .../riscv/amo-table-ztso-compare-exchange-7.c |   1 +
 .../riscv/amo-table-ztso-subword-amo-add-1.c  |   1 +
 .../riscv/amo-table-ztso-subword-amo-add-2.c  |   1 +
 .../riscv/amo-table-ztso-subword-amo-add-3.c  |   1 +
 .../riscv/amo-table-ztso-subword-amo-add-4.c  |   1 +
 .../riscv/amo-table-ztso-subword-amo-add-5.c  |   1 +
 gcc/testsuite/lib/target-supports.exp         | 134 ++++++++++++------
 35 files changed, 124 insertions(+), 61 deletions(-)

--
2.34.1

diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-1.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-1.c
index 8ab1a02b40c..9c2ba39789a 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-1.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-1.c
@@ -1,7 +1,7 @@
 /* { dg-do compile } */
 /* Verify that atomic op mappings match Table A.6's recommended mapping.  */
 /* { dg-options "-O3" } */
-/* { dg-add-options riscv_a } */
+/* { dg-add-options riscv_zaamo } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-2.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-2.c
index a5a841abdcd..b7682a5bab4 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-2.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-2.c
@@ -1,7 +1,7 @@
 /* { dg-do compile } */
 /* Verify that atomic op mappings match Table A.6's recommended mapping.  */
 /* { dg-options "-O3" } */
-/* { dg-add-options riscv_a } */
+/* { dg-add-options riscv_zaamo } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-3.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-3.c
index f523821b658..c8776872d91 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-3.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-3.c
@@ -1,7 +1,7 @@
 /* { dg-do compile } */
 /* Verify that atomic op mappings match Table A.6's recommended mapping.  */
 /* { dg-options "-O3" } */
-/* { dg-add-options riscv_a } */
+/* { dg-add-options riscv_zaamo } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-4.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-4.c
index f1561b52c89..b37c4c3f242 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-4.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-4.c
@@ -1,7 +1,7 @@
 /* { dg-do compile } */
 /* Verify that atomic op mappings match Table A.6's recommended mapping.  */
 /* { dg-options "-O3" } */
-/* { dg-add-options riscv_a } */
+/* { dg-add-options riscv_zaamo } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-5.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-5.c
index 81f876ee625..8d45ca7a347 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-5.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-5.c
@@ -1,7 +1,7 @@
 /* { dg-do compile } */
 /* Verify that atomic op mappings match Table A.6's recommended mapping.  */
 /* { dg-options "-O3" } */
-/* { dg-add-options riscv_a } */
+/* { dg-add-options riscv_zaamo } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-1.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-1.c
index dc445f0316a..4917cd6bd2b 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-1.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-1.c
@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* Verify that compare exchange mappings match Table A.6's recommended mapping.  */
-/* { dg-add-options riscv_a } */
+/* { dg-add-options riscv_zalrsc } */
 /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-2.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-2.c
index 7e8ab7bb5ef..121936507e3 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-2.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-2.c
@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* Verify that compare exchange mappings match Table A.6's recommended mapping.  */
-/* { dg-add-options riscv_a } */
+/* { dg-add-options riscv_zalrsc } */
 /* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-3.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-3.c
index 4cb6c422213..649c7d2b1fe 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-3.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-3.c
@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* Verify that compare exchange mappings match Table A.6's recommended mapping.  */
-/* { dg-add-options riscv_a } */
+/* { dg-add-options riscv_zalrsc } */
 /* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-4.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-4.c
index da81c34b92c..5f7fdeb1b21 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-4.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-4.c
@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* Verify that compare exchange mappings match Table A.6's recommended mapping.  */
-/* { dg-add-options riscv_a } */
+/* { dg-add-options riscv_zalrsc } */
 /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-5.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-5.c
index bb16ccc754c..f4bd7d6d842 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-5.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-5.c
@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* Verify that compare exchange mappings match Table A.6's recommended mapping.  */
-/* { dg-add-options riscv_a } */
+/* { dg-add-options riscv_zalrsc } */
 /* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-6.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-6.c
index 0f3f0b49d95..154764425ae 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-6.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-6.c
@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* Verify that compare exchange mappings match Table A.6's recommended mapping.  */
-/* { dg-add-options riscv_a } */
+/* { dg-add-options riscv_zalrsc } */
 /* Mixed mappings need to be unioned.  */
 /* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-7.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-7.c
index d51de56cc78..16712540919 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-7.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-7.c
@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* Verify that compare exchange mappings match Table A.6's recommended mapping.  */
-/* { dg-add-options riscv_a } */
+/* { dg-add-options riscv_zalrsc } */
 /* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-1.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-1.c
index ca8aa715bed..4174fdee352 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-1.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-1.c
@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* Verify that subword atomic op mappings match Table A.6's recommended mapping.  */
-/* { dg-add-options riscv_a } */
+/* { dg-add-options riscv_zalrsc } */
 /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-2.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-2.c
index e64759a54ae..4c06c90b558 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-2.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-2.c
@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* Verify that subword atomic op mappings match Table A.6's recommended mapping.  */
-/* { dg-add-options riscv_a } */
+/* { dg-add-options riscv_zalrsc } */
 /* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-3.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-3.c
index 9d3f69264fa..7e791c901b6 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-3.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-3.c
@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* Verify that subword atomic op mappings match Table A.6's recommended mapping.  */
-/* { dg-add-options riscv_a } */
+/* { dg-add-options riscv_zalrsc } */
 /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-4.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-4.c
index ba32ed59c2f..76f3be27110 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-4.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-4.c
@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* Verify that subword atomic op mappings match Table A.6's recommended mapping.  */
-/* { dg-add-options riscv_a } */
+/* { dg-add-options riscv_zalrsc } */
 /* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-5.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-5.c
index f9be8c5e628..8dbfa9c4fc8 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-5.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-5.c
@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* Verify that subword atomic op mappings match Table A.6's recommended mapping.  */
-/* { dg-add-options riscv_a } */
+/* { dg-add-options riscv_zalrsc } */
 /* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-1.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-1.c
index a9edc33ff39..6def4a46712 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-1.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-1.c
@@ -3,6 +3,7 @@
 /* { dg-options "-O3" } */
 /* { dg-add-options riscv_a } */
 /* { dg-add-options riscv_ztso } */
+/* { dg-add-options riscv_zaamo } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-2.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-2.c
index ad843402bcc..88850d7dc07 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-2.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-2.c
@@ -3,6 +3,7 @@
 /* { dg-options "-O3" } */
 /* { dg-add-options riscv_a } */
 /* { dg-add-options riscv_ztso } */
+/* { dg-add-options riscv_zaamo } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-3.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-3.c
index bdae5bb83a6..400c95d3e53 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-3.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-3.c
@@ -3,6 +3,7 @@
 /* { dg-options "-O3" } */
 /* { dg-add-options riscv_a } */
 /* { dg-add-options riscv_ztso } */
+/* { dg-add-options riscv_zaamo } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-4.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-4.c
index 815a72f1e56..cec3e5d1962 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-4.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-4.c
@@ -3,6 +3,7 @@
 /* { dg-options "-O3" } */
 /* { dg-add-options riscv_a } */
 /* { dg-add-options riscv_ztso } */
+/* { dg-add-options riscv_zaamo } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-5.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-5.c
index eda6f01096e..7bbe30b0d66 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-5.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-5.c
@@ -3,6 +3,7 @@
 /* { dg-options "-O3" } */
 /* { dg-add-options riscv_a } */
 /* { dg-add-options riscv_ztso } */
+/* { dg-add-options riscv_zaamo } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-1.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-1.c
index b6315c45e85..8f44ffd3eef 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-1.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-1.c
@@ -2,6 +2,7 @@
 /* Verify that compare exchange mappings match the Ztso suggested mapping.  */
 /* { dg-add-options riscv_a } */
 /* { dg-add-options riscv_ztso } */
+/* { dg-add-options riscv_zalrsc } */
 /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-2.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-2.c
index e487184f6cf..08942d777e6 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-2.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-2.c
@@ -2,6 +2,7 @@
 /* Verify that compare exchange mappings match the Ztso suggested mapping.  */
 /* { dg-add-options riscv_a } */
 /* { dg-add-options riscv_ztso } */
+/* { dg-add-options riscv_zalrsc } */
 /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-3.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-3.c
index e9c925f0923..47bbab11185 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-3.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-3.c
@@ -2,6 +2,7 @@
 /* Verify that compare exchange mappings match the Ztso suggested mapping.  */
 /* { dg-add-options riscv_a } */
 /* { dg-add-options riscv_ztso } */
+/* { dg-add-options riscv_zalrsc } */
 /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-4.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-4.c
index 6b454559633..197dc9b3fd5 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-4.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-4.c
@@ -2,6 +2,7 @@
 /* Verify that compare exchange mappings match the Ztso suggested mapping.  */
 /* { dg-add-options riscv_a } */
 /* { dg-add-options riscv_ztso } */
+/* { dg-add-options riscv_zalrsc } */
 /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-5.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-5.c
index 02c9f0ada77..8bf094286b3 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-5.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-5.c
@@ -2,6 +2,7 @@
 /* Verify that compare exchange mappings match the Ztso suggested mapping.  */
 /* { dg-add-options riscv_a } */
 /* { dg-add-options riscv_ztso } */
+/* { dg-add-options riscv_zalrsc } */
 /* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-6.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-6.c
index 75abd5d3dfb..4fe739197b6 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-6.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-6.c
@@ -2,6 +2,7 @@
 /* Verify that compare exchange mappings match the Ztso suggested mapping.  */
 /* { dg-add-options riscv_a } */
 /* { dg-add-options riscv_ztso } */
+/* { dg-add-options riscv_zalrsc } */
 /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-7.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-7.c
index 33928c0eac4..9107b5832d5 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-7.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-7.c
@@ -2,6 +2,7 @@
 /* Verify that compare exchange mappings match the Ztso suggested mapping.  */
 /* { dg-add-options riscv_a } */
 /* { dg-add-options riscv_ztso } */
+/* { dg-add-options riscv_zalrsc } */
 /* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-1.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-1.c
index 2a40d6b1376..5135e2ef25d 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-1.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-1.c
@@ -2,6 +2,7 @@
 /* Verify that subword atomic op mappings match the Ztso suggested mapping.  */
 /* { dg-add-options riscv_a } */
 /* { dg-add-options riscv_ztso } */
+/* { dg-add-options riscv_zalrsc } */
 /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-2.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-2.c
index c79380f2611..4a99833c34a 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-2.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-2.c
@@ -2,6 +2,7 @@
 /* Verify that subword atomic op mappings match the Ztso suggested mapping.  */
 /* { dg-add-options riscv_a } */
 /* { dg-add-options riscv_ztso } */
+/* { dg-add-options riscv_zalrsc } */
 /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-3.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-3.c
index d1a94eccfa8..c5a38418ca7 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-3.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-3.c
@@ -2,6 +2,7 @@
 /* Verify that subword atomic op mappings match the Ztso suggested mapping.  */
 /* { dg-add-options riscv_a } */
 /* { dg-add-options riscv_ztso } */
+/* { dg-add-options riscv_zalrsc } */
 /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-4.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-4.c
index 3d65bc2f64a..64fe80e767a 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-4.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-4.c
@@ -2,6 +2,7 @@
 /* Verify that subword atomic op mappings match the Ztso suggested mapping.  */
 /* { dg-add-options riscv_a } */
 /* { dg-add-options riscv_ztso } */
+/* { dg-add-options riscv_zalrsc } */
 /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-5.c b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-5.c
index 10354387a13..ac5b5d32c47 100644
--- a/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-5.c
+++ b/gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-5.c
@@ -2,6 +2,7 @@
 /* Verify that subword atomic op mappings match the Ztso suggested mapping.  */
 /* { dg-add-options riscv_a } */
 /* { dg-add-options riscv_ztso } */
+/* { dg-add-options riscv_zalrsc } */
 /* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */

diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index 836545b4e11..48d8375a07a 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -28,7 +28,7 @@
 # If ARGS is not empty, its first element is a string that
 # should be added to the command line.
 #
-# Assume by default that CONTENTS is C code.
+# Assume by default that CONTENTS is C code.
 # Otherwise, code should contain:
 # "/* Assembly" for assembly code,
 # "// C++" for c++,
@@ -39,12 +39,12 @@
 # "// Go" for Go
 # "// Rust" for Rust
 # and "(* Modula-2" for Modula-2
-# If the tool is ObjC/ObjC++ then we overide the extension to .m/.mm to
+# If the tool is ObjC/ObjC++ then we overide the extension to .m/.mm to
 # allow for ObjC/ObjC++ specific flags.

 proc check_compile {basename type contents args} {
     global tool
-    verbose "check_compile tool: $tool for $basename"
+    verbose "check_compile tool: $tool for $basename"

     # Save additional_sources to avoid compiling testsuite's sources
     # against check_compile's source.
@@ -100,7 +100,7 @@ proc check_compile {basename type contents args} {
     global compiler_flags
     set save_compiler_flags $compiler_flags
     set lines [${tool}_target_compile $src $output $compile_type "$options"]
-    set compiler_flags $save_compiler_flags
+    set compiler_flags $save_compiler_flags
     file delete $src

     set scan_output $output
@@ -569,7 +569,7 @@ proc check_ifunc_available { } {
    #endif
    extern void f_ ();
    typedef void F (void);
-   F* g (void) { return &f_; }
+   F* g (void) { return &f_; }
    void f () __attribute__ ((ifunc ("g")));
    #ifdef __cplusplus
    }
@@ -631,7 +631,7 @@ proc check_dot_available { } {

 # Return 1 if according to target_info struct and explicit target list
 # target is supposed to support trampolines.
-
+
 proc check_effective_target_trampolines { } {
     if [target_info exists gcc,no_trampolines] {
       return 0
@@ -695,7 +695,7 @@ proc check_effective_target_signal { } {
 # Return 1 if according to target_info struct and explicit target list
 # target disables -fdelete-null-pointer-checks.  Targets should return 0
 # if they simply default to -fno-delete-null-pointer-checks but obey
-# -fdelete-null-pointer-checks when passed explicitly (and tests that
+# -fdelete-null-pointer-checks when passed explicitly (and tests that
 # depend on this option should do that).

 proc check_effective_target_keeps_null_pointer_checks { } {
@@ -704,7 +704,7 @@ proc check_effective_target_keeps_null_pointer_checks { } {
     }
     if { [istarget msp430-*-*]
          || [istarget avr-*-*] } {
-   return 1;
+   return 1;
     }
     return 0
 }
@@ -716,7 +716,7 @@ proc check_effective_target_keeps_null_pointer_checks { } {
 # Each individual perf tries to grab it
 # This causes problems with parallel test suite runs. Instead
 # limit us to 8 pages (32K), which should be good enough
-# for the small test programs. With the default settings
+# for the small test programs. With the default settings
 # this allows parallelism of 16 and higher of parallel gcc-auto-profile
 proc profopt-perf-wrapper { } {
     global srcdir
@@ -831,7 +831,7 @@ proc check_profiling_available { test_what } {
         || [istarget powerpc-*-eabi*]
         || [istarget powerpc-*-elf]
         || [istarget pru-*-*]
-        || [istarget rx-*-*]
+        || [istarget rx-*-*]
         || [istarget tic6x-*-elf]
         || [istarget visium-*-*]
         || [istarget xstormy16-*]
@@ -1020,7 +1020,7 @@ proc check_effective_target_tls_native {} {
     if { [istarget *-*-vxworks*] } {
    return 0
     }
-
+
     return [check_no_messages_and_pattern tls_native "!emutls" assembly {
    __thread int i;
    int f (void) { return i; }
@@ -1036,7 +1036,7 @@ proc check_effective_target_tls_emulated {} {
     if { [istarget *-*-vxworks*] } {
    return 1
     }
-
+
     return [check_no_messages_and_pattern tls_emulated "emutls" assembly {
    __thread int i;
    int f (void) { return i; }
@@ -1082,7 +1082,7 @@ proc check_effective_target_function_sections {} {
     if { [istarget *-*-darwin*] } {
    return 0
     }
-
+
     return [check_no_compiler_messages functionsections assembly {
    void foo (void) { }
     } "-ffunction-sections"]
@@ -1104,7 +1104,7 @@ proc check_effective_target_trapping {} {
     } "-ftrapv"]
 }

-# Return 1 if compilation with -fgraphite is error-free for trivial
+# Return 1 if compilation with -fgraphite is error-free for trivial
 # code, 0 otherwise.

 proc check_effective_target_fgraphite {} {
@@ -1737,7 +1737,7 @@ proc check_effective_target_fortran_real_10 { } {
 # 0 otherwise.  This differs from check_effective_target_fortran_real_16
 # because _Float128 has the additional requirement that it be the
 # 128-bit IEEE encoding; even if _Float128 is available in C, it may not
-# have a corresponding Fortran kind on targets (PowerPC) that use some
+# have a corresponding Fortran kind on targets (PowerPC) that use some
 # other encoding for long double/TFmode/real(16).
 proc check_effective_target_fortran_real_c_float128 { } {
     return [check_no_compiler_messages fortran_real_c_float128 executable {
@@ -1889,6 +1889,28 @@ proc check_effective_target_riscv_a { } {
     }]
 }

+# Return 1 if the target arch supports the atomic LRSC extension, 0 otherwise.
+# Cache the result.
+
+proc check_effective_target_riscv_zalrsc { } {
+    return [check_no_compiler_messages riscv_ext_zalrsc assembly {
+       #ifndef __riscv_zalrsc
+       #error "Not __riscv_zalrsc"
+       #endif
+    }]
+}
+
+# Return 1 if the target arch supports the atomic AMO extension, 0 otherwise.
+# Cache the result.
+
+proc check_effective_target_riscv_zaamo { } {
+    return [check_no_compiler_messages riscv_ext_zaamo assembly {
+       #ifndef __riscv_zaamo
+       #error "Not __riscv_zaamo"
+       #endif
+    }]
+}
+
 # Return 1 if the target arch supports the double precision floating point
 # extension, 0 otherwise.  Cache the result.

@@ -2010,7 +2032,7 @@ proc check_effective_target_riscv_v_ok { } {
 proc check_effective_target_riscv_zfh_ok { } {
     # If the target already supports zfh without any added options,
     # we may assume we can execute just fine.
-    # ??? Other cases we should consider:
+    # ??? Other cases we should consider:
     # - target / simulator already supports zfh extension - test for that.
     # - target is a simulator, and dg-add-options knows how to enable zfh support in that simulator
     if { [check_effective_target_riscv_zfh] } {
@@ -2083,7 +2105,7 @@ proc check_effective_target_riscv_zvbb_ok { } {
 proc riscv_get_arch { } {
     set gcc_march ""
     # ??? do we neeed to add more extensions to the list below?
-    foreach ext { i m a f d q c v zicsr zifencei zfh zba zbb zbc zbs zvbb zvfh ztso } {
+    foreach ext { i m a f d q c v zicsr zifencei zfh zba zbb zbc zbs zvbb zvfh ztso zaamo zalrsc } {
    if { [check_no_compiler_messages  riscv_ext_$ext assembly [string map [list DEF __riscv_$ext] {
        #ifndef DEF
        #error "Not DEF"
@@ -2142,6 +2164,30 @@ proc add_options_for_riscv_v { flags } {
     return "$flags -march=[regsub {[[:alnum:]]*} [riscv_get_arch] &v]"
 }

+proc add_options_for_riscv_zaamo { flags } {
+    if { [lsearch $flags -march=*] >= 0 } {
+   # If there are multiple -march flags, we have to adjust all of them.
+   set flags [regsub -all -- {(?:^|[[:space:]])-march=[[:alnum:]_.]*} $flags &_zaamo ]
+   return [regsub -all -- {((?:^|[[:space:]])-march=[[:alnum:]_.]*_zaamo[[:alnum:]_.]*)_zaamo} $flags \\1 ]
+    }
+    if { [check_effective_target_riscv_zaamo] } {
+   return "$flags"
+    }
+    return "$flags -march=[riscv_get_arch]_zaamo"
+}
+
+proc add_options_for_riscv_zalrsc { flags } {
+    if { [lsearch $flags -march=*] >= 0 } {
+   # If there are multiple -march flags, we have to adjust all of them.
+   set flags [regsub -all -- {(?:^|[[:space:]])-march=[[:alnum:]_.]*} $flags &_zalrsc ]
+   return [regsub -all -- {((?:^|[[:space:]])-march=[[:alnum:]_.]*_zalrsc[[:alnum:]_.]*)_zalrsc} $flags \\1 ]
+    }
+    if { [check_effective_target_riscv_zalrsc] } {
+   return "$flags"
+    }
+    return "$flags -march=[riscv_get_arch]_zalrsc"
+}
+
 proc add_options_for_riscv_zfh { flags } {
     if { [lsearch $flags -march=*] >= 0 } {
    # If there are multiple -march flags, we have to adjust all of them.
@@ -2945,7 +2991,7 @@ proc check_effective_target_long_double_ieee128 { } {
    int main()
    {
      _Float128 a2;
-     long double b2;
+     long double b2;
      if (sizeof (long double) != 16)
        return 1;
      b = one + two;
@@ -3409,7 +3455,7 @@ proc check_effective_target_ptr32plus { } {
     if { [istarget msp430-*-*] } {
         return 0
     }
-
+
     return [check_no_compiler_messages ptr32plus object {
    int dummy[sizeof (void *) >= 4 ? 1 : -1];
     }]
@@ -4299,7 +4345,7 @@ proc check_effective_target_int128 { } {
     }]
 }

-# Return 1 if the target supports unsigned int->float conversion
+# Return 1 if the target supports unsigned int->float conversion
 #

 proc check_effective_target_vect_uintfloat_cvt { } {
@@ -5327,7 +5373,7 @@ proc check_effective_target_arm_neonv2_ok_nocache { } {
    foreach flags {"" "-mfloat-abi=softfp" "-mfpu=neon-vfpv4" "-mfpu=neon-vfpv4 -mfloat-abi=softfp"} {
        if { [check_no_compiler_messages_nocache arm_neonv2_ok object {
        #include "arm_neon.h"
-       float32x2_t
+       float32x2_t
        foo (float32x2_t a, float32x2_t b, float32x2_t c)
                 {
                   return vfma_f32 (a, b, c);
@@ -7840,7 +7886,7 @@ proc check_effective_target_vect_widen_sum_hi_to_si { } {
 # promotion (unpacking) from chars to shorts.
 #
 # This won't change for different subtargets so cache the result.
-
+
 proc check_effective_target_vect_widen_sum_qi_to_hi { } {
     return [check_cached_effective_target_indexed vect_widen_sum_qi_to_hi {
       expr { [check_effective_target_vect_unpack]
@@ -7854,7 +7900,7 @@ proc check_effective_target_vect_widen_sum_qi_to_hi { } {
 # widening summation of *char* args into *int* result, 0 otherwise.
 #
 # This won't change for different subtargets so cache the result.
-
+
 proc check_effective_target_vect_widen_sum_qi_to_si { } {
     return [check_cached_effective_target_indexed vect_widen_sum_qi_to_si {
       expr { [istarget powerpc*-*-*]
@@ -7880,7 +7926,7 @@ proc check_effective_target_vect_widen_mult_qi_to_hi { } {
              && ![check_effective_target_aarch64_sve])
          || [is-effective-target arm_neon]
          || ([istarget s390*-*-*]
-             && [check_effective_target_s390_vx]))
+             && [check_effective_target_s390_vx]))
          || [istarget amdgcn-*-*] }}]
 }

@@ -8045,7 +8091,7 @@ proc check_effective_target_vect_udot_hi { } {
         || ([istarget mips*-*-*]
         && [et-is-effective-target mips_msa])
         || ([istarget riscv*-*-*]
-        && [check_effective_target_riscv_v])
+        && [check_effective_target_riscv_v])
         || ([istarget loongarch*-*-*]
         && [check_effective_target_loongarch_sx]) }}]
 }
@@ -8099,11 +8145,11 @@ proc check_effective_target_vect_sdiv_pow2_si {} {
 }

 # Return 1 if the target plus current options supports a vector
-# demotion (packing) of shorts (to chars) and ints (to shorts)
+# demotion (packing) of shorts (to chars) and ints (to shorts)
 # using modulo arithmetic, 0 otherwise.
 #
 # This won't change for different subtargets so cache the result.
-
+
 proc check_effective_target_vect_pack_trunc { } {
     return [check_cached_effective_target_indexed vect_pack_trunc {
       expr { [istarget powerpc*-*-*]
@@ -8126,7 +8172,7 @@ proc check_effective_target_vect_pack_trunc { } {
 # promotion (unpacking) of chars (to shorts) and shorts (to ints), 0 otherwise.
 #
 # This won't change for different subtargets so cache the result.
-
+
 proc check_effective_target_vect_unpack { } {
     return [check_cached_effective_target_indexed vect_unpack {
       expr { ([istarget powerpc*-*-*] && ![istarget powerpc-*paired*])
@@ -8735,7 +8781,7 @@ proc check_effective_target_vector_alignment_reachable { } {

 proc check_effective_target_vector_alignment_reachable_for_64bit { } {
     set et_vector_alignment_reachable_for_64bit 0
-    if { [check_effective_target_vect_aligned_arrays]
+    if { [check_effective_target_vect_aligned_arrays]
     || [check_effective_target_natural_alignment_64] } {
    set et_vector_alignment_reachable_for_64bit 1
     }
@@ -8836,7 +8882,7 @@ proc check_effective_target_vect_cond_mixed { } {
     return [check_cached_effective_target_indexed vect_cond_mixed {
       expr { [istarget i?86-*-*] || [istarget x86_64-*-*]
         || [istarget aarch64*-*-*]
-        || [istarget powerpc*-*-*]
+        || [istarget powerpc*-*-*]
         || ([istarget arm*-*-*]
         && [check_effective_target_arm_neon_ok])
         || ([istarget mips*-*-*]
@@ -9509,14 +9555,14 @@ proc check_effective_target_sync_int_long { } {
       expr { [istarget ia64-*-*]
         || [istarget i?86-*-*] || [istarget x86_64-*-*]
         || [istarget aarch64*-*-*]
-        || [istarget alpha*-*-*]
-        || [istarget arm*-*-linux-*]
-        || [istarget arm*-*-uclinuxfdpiceabi]
+        || [istarget alpha*-*-*]
+        || [istarget arm*-*-linux-*]
+        || [istarget arm*-*-uclinuxfdpiceabi]
         || ([istarget arm*-*-*]
         && [check_effective_target_arm_acq_rel])
         || [istarget bfin*-*linux*]
         || [istarget hppa*-*linux*]
-        || [istarget s390*-*-*]
+        || [istarget s390*-*-*]
         || [istarget powerpc*-*-*]
         || [istarget cris-*-*]
         || ([istarget sparc*-*-*] && [check_effective_target_sparc_v9])
@@ -9532,7 +9578,7 @@ proc check_effective_target_sync_int_long { } {
 proc check_effective_target_sync_int_long_stack { } {
     return [check_cached_effective_target sync_int_long_stack {
       expr { ![istarget nvptx*-*-*]
-        && [check_effective_target_sync_int_long]
+        && [check_effective_target_sync_int_long]
     }}]
 }

@@ -9545,13 +9591,13 @@ proc check_effective_target_sync_char_short { } {
       expr { [istarget aarch64*-*-*]
         || [istarget ia64-*-*]
         || [istarget i?86-*-*] || [istarget x86_64-*-*]
-        || [istarget alpha*-*-*]
-        || [istarget arm*-*-linux-*]
-        || [istarget arm*-*-uclinuxfdpiceabi]
+        || [istarget alpha*-*-*]
+        || [istarget arm*-*-linux-*]
+        || [istarget arm*-*-uclinuxfdpiceabi]
         || ([istarget arm*-*-*]
         && [check_effective_target_arm_acq_rel])
         || [istarget hppa*-*linux*]
-        || [istarget s390*-*-*]
+        || [istarget s390*-*-*]
         || [istarget powerpc*-*-*]
         || [istarget cris-*-*]
         || ([istarget sparc*-*-*] && [check_effective_target_sparc_v9])
@@ -10443,7 +10489,7 @@ proc check_effective_target_sse { } {
 proc check_effective_target_sse2 { } {
     return [check_no_compiler_messages sse2 object {
    typedef long long __m128i __attribute__ ((__vector_size__ (16)));
-
+
    __m128i _mm_srli_si128 (__m128i __A, int __N)
    {
        return (__m128i)__builtin_ia32_psrldqi128 (__A, 8);
@@ -12512,14 +12558,14 @@ proc check_effective_target_autoincdec { } {
 #
 # This is used to restrict the stack-clash mitigation tests to
 # just those targets that have been explicitly supported.
-#
+#
 # In addition to the prologue work on those targets, each target's
 # properties should be described in the functions below so that
 # tests do not become a mess of unreadable target conditions.
-#
+#
 proc check_effective_target_supports_stack_clash_protection { } {

-    if { [istarget x86_64-*-*] || [istarget i?86-*-*]
+    if { [istarget x86_64-*-*] || [istarget i?86-*-*]
      || [istarget powerpc*-*-*] || [istarget rs6000*-*-*]
      || [istarget aarch64*-**] || [istarget s390*-*-*]
      || [istarget loongarch64*-**] } {
@@ -13212,7 +13258,7 @@ main:
    .byte 0
   } ""]
 }
-
+
 # Return 1 if this target has prog named "$prog", 0 otherwise.

 proc check_is_prog_name_available { prog } {

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