ewlu / gcc-precommit-ci

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Patch Status 37289-回复PATCH_v1_RISCV_Bugfix_incorrect_operand_for_vwsll_autovect-1 #2043

Closed github-actions[bot] closed 1 month ago

github-actions[bot] commented 3 months ago

Precommit CI Run information

Logs can be found in the associated Github Actions run: https://github.com/ewlu/gcc-precommit-ci/actions/runs/10331803954

Patch information

Applied patches: 1 -> 1 Associated series: https://patchwork.sourceware.org/project/gcc/list/?series=37289 Last patch applied: https://patchwork.sourceware.org/project/gcc/patch/tencent_5A1797F672C748F22E9E1014@qq.com/ Patch id: 95619

Build Targets

Some targets are built as multilibs. If a build target ends with multilib, please refer to the table below to see all the targets within that multilib. Target name -march string
newlib-rv64gcv-lp64d-multilib rv64gcv-lp64d, rv32gc-ilp32d, rv64gc-lp64d, rv32imc_zba_zbb_zbc_zbs-ilp32
linux-rv64gcv-lp64d-multilib rv32gcv-ilp32d, rv64gcv-lp64d
linux-rv64gc_zba_zbb_zbc_zbs-lp64d-multilib rv32gc_zba_zbb_zbc_zbs-ilp32d, rv64gc_zba_zbb_zbc_zbs-lp64d

Target Information

Target Shorthand -march string
Bitmanip gc_zba_zbb_zbc_zbs

Notes

Testsuite results use a more lenient allowlist to reduce error reporting with flakey tests. Please take a look at the current allowlist. Results come from a sum file comparator. Each patch is applied to a well known, non-broken baseline taken from our gcc postcommit framework (here) which runs the full gcc testsuite every 6 hours. If you have any questions or encounter any issues which may seem like false-positives, please contact us at patchworks-ci@rivosinc.com

github-actions[bot] commented 3 months ago

Lint Status

The following issues have been found with 37289-回复PATCH_v1_RISCV_Bugfix_incorrect_operand_for_vwsll_autovect-1 using gcc's ./contrib/check_GNU_style.py. Please use your best judgement when resolving these issues. These are only warnings and do not need to be resolved in order to merge your patch.

Traceback (most recent call last):
  File "./gcc/contrib/check_GNU_style.py", line 45, in <module>
    main()
  File "./gcc/contrib/check_GNU_style.py", line 43, in main
    check_GNU_style_file(diff_file, format)
  File "/home/runner/work/gcc-precommit-ci/gcc-precommit-ci/riscv-gnu-toolchain/gcc/contrib/check_GNU_style_lib.py", line 279, in check_GNU_style_file
    patch = PatchSet(file)
  File "/home/runner/.local/lib/python3.8/site-packages/unidiff/patch.py", line 462, in __init__
    self._parse(data, encoding=encoding, metadata_only=metadata_only)
  File "/home/runner/.local/lib/python3.8/site-packages/unidiff/patch.py", line 552, in _parse
    current_file._parse_hunk(line, diff, encoding, metadata_only)
  File "/home/runner/.local/lib/python3.8/site-packages/unidiff/patch.py", line 318, in _parse_hunk
    raise UnidiffParseError(
unidiff.errors.UnidiffParseError: Hunk diff line expected: &nbsp;&nbsp; "&amp;&amp; 1"

Additional information

github-actions[bot] commented 3 months ago

Apply Status

Target Status
Baseline hash: https://github.com/gcc-mirror/gcc/commit/8cc67b520968ca9a13fd96896522aa66e39a99e2 Failed
Tip of tree hash: https://github.com/gcc-mirror/gcc/commit/16ce78156d822f3d26b182785111d8f77fa7a392 Failed

Command

> git am ../patches/*.patch --whitespace=fix -q --3way --empty=drop

Output

error: corrupt patch at line 17
error: could not build fake ancestor
hint: Use 'git am --show-current-patch=diff' to see the failed patch
hint: When you have resolved this problem, run "git am --continue".
hint: If you prefer to skip this patch, run "git am --skip" instead.
hint: To restore the original branch and stop patching, run "git am --abort".
hint: Disable this message with "git config advice.mergeConflict false"
Patch failed at 0001 回复:[PATCH v1] RISC-V: Bugfix incorrect operand for vwsll auto-vect
---
&nbsp;gcc/config/riscv/autovec-opt.md&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; |&nbsp; 4 ++++
&nbsp;.../gcc.target/riscv/rvv/base/pr116280-1.c&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; | 14 ++++++++++++++
&nbsp;.../gcc.target/riscv/rvv/base/pr116280-2.c&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; | 10 ++++++++++
&nbsp;3 files changed, 28 insertions(+)
&nbsp;create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr116280-1.c
&nbsp;create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr116280-2.c

-- 
2.43.0

diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
index d7a3cfd4602..4b33a145c17 100644
--- a/gcc/config/riscv/autovec-opt.md
+++ b/gcc/config/riscv/autovec-opt.md
@@ -1546,6 +1546,10 @@ (define_insn_and_split "*vwsll_zext1_trunc_<mode&gt;"
&nbsp;&nbsp; "&amp;&amp; 1"
&nbsp;&nbsp; [(const_int 0)]
&nbsp;&nbsp; {
+&nbsp;&nbsp;&nbsp; rtx truncated = gen_reg_rtx (<V_QUAD_TRUNC&gt;mode);
+&nbsp;&nbsp;&nbsp; emit_insn (gen_trunc<mode&gt;<v_quad_trunc&gt;2 (truncated, operands[2]));
+&nbsp;&nbsp;&nbsp; operands[2] = truncated;
+
&nbsp;&nbsp;&nbsp;&nbsp; insn_code icode = code_for_pred_vwsll (<V_DOUBLE_TRUNC&gt;mode);
&nbsp;&nbsp;&nbsp;&nbsp; riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP, operands);
&nbsp;&nbsp;&nbsp;&nbsp; DONE;
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr116280-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr116280-1.c
new file mode 100644
index 00000000000..8b8547e2c34
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr116280-1.c
@@ -0,0 +1,14 @@
+/* Test there is no ICE when compile.&nbsp; */
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvbb -mabi=lp64d -O3" } */
+
+short a;
+char b;
+
+void
+test (int e[][1][1], char f[][1][1][1][1]) {
+&nbsp; for (int g; b;)
+&nbsp;&nbsp;&nbsp; for (;;)
+&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; for (int h; h < 4073709551572ULL; h += 18446744073709551612U)
+&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; a = f[2][2][1][4073709551612][1] << e[1][1][g];
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr116280-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr116280-2.c
new file mode 100644
index 00000000000..02f2de66eff
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr116280-2.c
@@ -0,0 +1,10 @@
+/* Test there is no ICE when compile.&nbsp; */
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvbb -mabi=lp64d -O3" } */
+
+void
+test (short *restrict dst, char *restrict a, int *restrict b, int n)
+{
+&nbsp; for (int i = 0; i < n; i++)
+&nbsp;&nbsp;&nbsp; dst[i] = a[i] << b[i];
+}

Additional information