Patch Status 27150-RISCV_Support_XTheadVector_extensions-4

github-actions[bot] commented 8 months ago

Precommit CI Run information

Logs can be found in the associated Github Actions run: https://github.com/ewlu/gcc-precommit-ci/actions/runs/6911917152

Patch information

Applied patches: 1 -> 4 Associated series: https://patchwork.sourceware.org/project/gcc/list/?series=27150 Last patch applied: https://patchwork.sourceware.org/project/gcc/patch/20231118043227.3757-1-cooper.joshua@linux.alibaba.com/ Patch id: 80202

Build Targets

Some targets are built as multilibs. If a build target ends with `multilib`, please refer to the table below to see all the targets within that multilib.	Target name	`-march` string
newlib-rv64gc-lp64d-multilib	`rv32gc-ilp32d`, `rv64gc-lp64d`
newlib-rv64gcv-lp64d-multilib	`rv64gcv-lp64d`
linux-rv64gcv-lp64d-multilib	`rv32gcv-ilp32d`, `rv64gcv-lp64d`

Target Information

Target Shorthand	`-march` string
Bitmanip	`gc_zba_zbb_zbc_zbs`

Notes

Testsuite checks are in beta testing stages. Results are unstable and may be inaccurate.

github-actions[bot] commented 8 months ago

Lint Status

The following issues have been found with 27150-RISCV_Support_XTheadVector_extensions-4 using gcc's ./contrib/check_GNU_style.py. Please use your best judgement when resolving these issues. These are only warnings and do not need to be resolved in order to merge your patch. If any of these warnings seem like false-positives that could be guarded against please contact me: patchworks-ci@rivosinc.com.

=== ERROR type #1: lines should not exceed 80 characters (45 error(s)) ===
gcc/config/riscv/vector.md:1102:80:   * return TARGET_XTHEADVECTOR ? \"th.vl%m1re.v\t%0,%1\" : \"vl%m1re<sew>.v\t%0,%1\";
gcc/config/riscv/vector.md:1723:80:   * return TARGET_XTHEADVECTOR ? \"th.vle.v\t%0,%3%p1\" : \"vle<sew>.v\t%0,%3%p1\";
gcc/config/riscv/vector.md:1725:80:   * return TARGET_XTHEADVECTOR ? \"th.vle.v\t%0,%3,%1.t\" : \"vle<sew>.v\t%0,%3,%1.t\";
gcc/config/riscv/vector.md:1726:80:   * return TARGET_XTHEADVECTOR ? \"th.vse.v\t%3,%0%p1\" : \"vse<sew>.v\t%3,%0%p1\";
gcc/config/riscv/vector.md:1752:80:  { return TARGET_XTHEADVECTOR ? "th.vse.v\t%2,%0%p1" : "vse<sew>.v\t%2,%0%p1"; }
gcc/config/riscv/vector.md:2009:80:   * return TARGET_XTHEADVECTOR ? \"th.vlse.v\t%0,%3,zero,%1.t\" : \"vlse<sew>.v\t%0,%3,zero,%1.t\";
gcc/config/riscv/vector.md:2010:80:   * return TARGET_XTHEADVECTOR ? \"th.vlse.v\t%0,%3,zero,%1.t\" : \"vlse<sew>.v\t%0,%3,zero,%1.t\";
gcc/config/riscv/vector.md:2011:80:   * return TARGET_XTHEADVECTOR ? \"th.vlse.v\t%0,%3,zero\" : \"vlse<sew>.v\t%0,%3,zero\";
gcc/config/riscv/vector.md:2012:80:   * return TARGET_XTHEADVECTOR ? \"th.vlse.v\t%0,%3,zero\" : \"vlse<sew>.v\t%0,%3,zero\";
gcc/config/riscv/vector.md:2070:80:   * return TARGET_XTHEADVECTOR ? \"th.vlse.v\t%0,%3,zero,%1.t\" : \"vlse<sew>.v\t%0,%3,zero,%1.t\";
gcc/config/riscv/vector.md:2071:80:   * return TARGET_XTHEADVECTOR ? \"th.vlse.v\t%0,%3,zero,%1.t\" : \"vlse<sew>.v\t%0,%3,zero,%1.t\";
gcc/config/riscv/vector.md:2072:80:   * return TARGET_XTHEADVECTOR ? \"th.vlse.v\t%0,%3,zero\" : \"vlse<sew>.v\t%0,%3,zero\";
gcc/config/riscv/vector.md:2073:80:   * return TARGET_XTHEADVECTOR ? \"th.vlse.v\t%0,%3,zero\" : \"vlse<sew>.v\t%0,%3,zero\";
gcc/config/riscv/vector.md:2165:80:  * return TARGET_XTHEADVECTOR ? \"th.vlse.v\t%0,%3,%z4%p1\" : \"vlse<sew>.v\t%0,%3,%z4%p1\";
gcc/config/riscv/vector.md:2166:80:  * return TARGET_XTHEADVECTOR ? \"th.vlse.v\t%0,%3,%z4\" : \"vlse<sew>.v\t%0,%3,%z4\";
gcc/config/riscv/vector.md:2167:80:  * return TARGET_XTHEADVECTOR ? \"th.vlse.v\t%0,%3,%z4,%1.t\" : \"vlse<sew>.v\t%0,%3,%z4,%1.t\";
gcc/config/riscv/vector.md:2168:80:  * return TARGET_XTHEADVECTOR ? \"th.vle.v\t%0,%3%p1\" : \"vle<sew>.v\t%0,%3%p1\";
gcc/config/riscv/vector.md:2170:80:  * return TARGET_XTHEADVECTOR ? \"th.vle.v\t%0,%3,%1.t\" : \"vle<sew>.v\t%0,%3,%1.t\";"
gcc/config/riscv/vector.md:2189:80:  * return TARGET_XTHEADVECTOR ? \"th.vsse.v\t%3,%0,%z2%p1\" : \"vsse<sew>.v\t%3,%0,%z2%p1\";
gcc/config/riscv/vector.md:2190:80:  * return TARGET_XTHEADVECTOR ? \"th.vse.v\t%3,%0%p1\" : \"vse<sew>.v\t%3,%0%p1\";"
gcc/config/riscv/vector.md:2220:80:  { return TARGET_XTHEADVECTOR ? "th.vlxe.v\t%0,(%z3),%4%p1" : "vl<order>xei<sew>.v\t%0,(%z3),%4%p1"; }
gcc/config/riscv/vector.md:3690:80:  { return TARGET_XTHEADVECTOR ? "th.vrsub.vx\t%0,%3,x0%p1" : "vneg.v\t%0,%3%p1"; }
gcc/config/riscv/vector.md:6091:80:  { return TARGET_XTHEADVECTOR ? "th.vmpopc.m\t%0,%2%p1" : "vcpop.m\t%0,%2%p1"; }
gcc/config/riscv/vector.md:6109:80:  { return TARGET_XTHEADVECTOR ? "th.vmfirst.m\t%0,%2%p1" : "vfirst.m\t%0,%2%p1"; }
gcc/config/riscv/vector.md:7749:80:  { return TARGET_XTHEADVECTOR ? "th.vfncvt.x<v_su>.f.v\t%0,%3%p1" : "vfncvt.x<v_su>.f.w\t%0,%3%p1"; }
gcc/config/riscv/vector.md:7791:80:  { return TARGET_XTHEADVECTOR ? "th.vfncvt.f.x<u>.v\t%0,%3%p1" : "vfncvt.f.x<u>.w\t%0,%3%p1"; }
gcc/config/riscv/vector.md:7814:80:  { return TARGET_XTHEADVECTOR ? "th.vfncvt.f.f.v\t%0,%3%p1" : "vfncvt.f.f.w\t%0,%3%p1"; }
gcc/config/riscv/vector.md:8314:80:  { return TARGET_XTHEADVECTOR ? "th.vleff.v\t%0,%3%p1" : "vle<sew>ff.v\t%0,%3%p1"; }
gcc/config/riscv/vector.md:8344:80:  { return TARGET_XTHEADVECTOR ? "th.vlseg<nf>e.v\t%0,(%z3)%p1" : "vlseg<nf>e<sew>.v\t%0,(%z3)%p1"; }
gcc/config/riscv/vector.md:8361:80:  { return TARGET_XTHEADVECTOR ? "th.vsseg<nf>e.v\t%2,(%z1)%p0" : "vsseg<nf>e<sew>.v\t%2,(%z1)%p0"; }
gcc/config/riscv/vector.md:8382:80:  { return TARGET_XTHEADVECTOR ? "th.vlsseg<nf>e.v\t%0,(%z3),%z4%p1" : "vlsseg<nf>e<sew>.v\t%0,(%z3),%z4%p1"; }
gcc/config/riscv/vector.md:8400:80:  { return TARGET_XTHEADVECTOR ? "th.vssseg<nf>e.v\t%3,(%z1),%z2%p0" : "vssseg<nf>e<sew>.v\t%3,(%z1),%z2%p0"; }
gcc/config/riscv/vector.md:8431:80:  { return TARGET_XTHEADVECTOR ? "th.vlseg<nf>eff.v\t%0,(%z3)%p1" : "vlseg<nf>e<sew>ff.v\t%0,(%z3)%p1"; }
gcc/config/riscv/vector.md:8452:80:  { return TARGET_XTHEADVECTOR ? "th.vlxseg<nf>e.v\t%0,(%z3),%4%p1" : "vl<order>xseg<nf>ei<RATIO64I:sew>.v\t%0,(%z3),%4%p1"; }
gcc/config/riscv/vector.md:8473:80:  { return TARGET_XTHEADVECTOR ? "th.vlxseg<nf>e.v\t%0,(%z3),%4%p1" : "vl<order>xseg<nf>ei<RATIO32I:sew>.v\t%0,(%z3),%4%p1"; }
gcc/config/riscv/vector.md:8494:80:  { return TARGET_XTHEADVECTOR ? "th.vlxseg<nf>e.v\t%0,(%z3),%4%p1" : "vl<order>xseg<nf>ei<RATIO16I:sew>.v\t%0,(%z3),%4%p1"; }
gcc/config/riscv/vector.md:8515:80:  { return TARGET_XTHEADVECTOR ? "th.vlxseg<nf>e.v\t%0,(%z3),%4%p1" : "vl<order>xseg<nf>ei<RATIO8I:sew>.v\t%0,(%z3),%4%p1"; }
gcc/config/riscv/vector.md:8536:80:  { return TARGET_XTHEADVECTOR ? "th.vlxseg<nf>e.v\t%0,(%z3),%4%p1" : "vl<order>xseg<nf>ei<RATIO4I:sew>.v\t%0,(%z3),%4%p1"; }
gcc/config/riscv/vector.md:8557:80:  { return TARGET_XTHEADVECTOR ? "th.vlxseg<nf>e.v\t%0,(%z3),%4%p1" : "vl<order>xseg<nf>ei<RATIO2I:sew>.v\t%0,(%z3),%4%p1"; }
gcc/config/riscv/vector.md:8574:80:  { return TARGET_XTHEADVECTOR ? "th.vsxseg<nf>e.v\t%3,(%z1),%2%p0" : "vs<order>xseg<nf>ei<RATIO64I:sew>.v\t%3,(%z1),%2%p0"; }
gcc/config/riscv/vector.md:8591:80:  { return TARGET_XTHEADVECTOR ? "th.vsxseg<nf>e.v\t%3,(%z1),%2%p0" : "vs<order>xseg<nf>ei<RATIO32I:sew>.v\t%3,(%z1),%2%p0"; }
gcc/config/riscv/vector.md:8608:80:  { return TARGET_XTHEADVECTOR ? "th.vsxseg<nf>e.v\t%3,(%z1),%2%p0" : "vs<order>xseg<nf>ei<RATIO16I:sew>.v\t%3,(%z1),%2%p0"; }
gcc/config/riscv/vector.md:8625:80:  { return TARGET_XTHEADVECTOR ? "th.vsxseg<nf>e.v\t%3,(%z1),%2%p0" : "vs<order>xseg<nf>ei<RATIO8I:sew>.v\t%3,(%z1),%2%p0"; }
gcc/config/riscv/vector.md:8642:80:  { return TARGET_XTHEADVECTOR ? "th.vsxseg<nf>e.v\t%3,(%z1),%2%p0" : "vs<order>xseg<nf>ei<RATIO4I:sew>.v\t%3,(%z1),%2%p0"; }
gcc/config/riscv/vector.md:8659:80:  { return TARGET_XTHEADVECTOR ? "th.vsxseg<nf>e.v\t%3,(%z1),%2%p0" : "vs<order>xseg<nf>ei<RATIO2I:sew>.v\t%3,(%z1),%2%p0"; }

=== ERROR type #2: trailing operator (1 error(s)) ===
gcc/config/riscv/riscv_th_vector.h:39:71:   not define the RVV types and intrinsic functions directly in C and C++

Additional information

github-actions[bot] commented 8 months ago

Apply Status

Target	Status
Baseline hash: https://github.com/gcc-mirror/gcc/commit/bc274b8d677212fbfc317d379acb02e0eef696a0	Failed
Tip of tree hash: https://github.com/gcc-mirror/gcc/commit/841008d3966c0fe7a80ec10703a50fbdab7620ac	Failed

Command

> git am ../patches/*.patch --whitespace=fix -q --3way --empty=drop

Output

error: sha1 information is lacking or useless (gcc/config/riscv/riscv-c.cc).
error: could not build fake ancestor
hint: Use 'git am --show-current-patch=diff' to see the failed patch
Patch failed at 0002 RISC-V: Handle differences between xtheadvector and vector
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
---
 gcc/config.gcc                                |   2 +-
 gcc/config/riscv/riscv-c.cc                   |   4 +-
 gcc/config/riscv/riscv.cc                     |  11 +-
 gcc/config/riscv/riscv_th_vector.h            |  49 ++
 gcc/config/riscv/vector-iterators.md          |   4 +
 gcc/config/riscv/vector.md                    | 777 +++++++++---------
 .../gcc.target/riscv/rvv/base/pragma-1.c      |   2 +-
 7 files changed, 466 insertions(+), 383 deletions(-)
 create mode 100644 gcc/config/riscv/riscv_th_vector.h

diff --git a/gcc/config.gcc b/gcc/config.gcc
index ba6d63e33ac..e0fc2b1a27c 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -548,7 +548,7 @@ riscv*)
    extra_objs="${extra_objs} riscv-vector-builtins.o riscv-vector-builtins-shapes.o riscv-vector-builtins-bases.o"
    extra_objs="${extra_objs} thead.o"
    d_target_objs="riscv-d.o"
-   extra_headers="riscv_vector.h"
+   extra_headers="riscv_vector.h riscv_th_vector.h"
    target_gtfiles="$target_gtfiles \$(srcdir)/config/riscv/riscv-vector-builtins.cc"
    target_gtfiles="$target_gtfiles \$(srcdir)/config/riscv/riscv-vector-builtins.h"
    ;;
diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc
index 184fff905b2..0a17d5f6656 100644
--- a/gcc/config/riscv/riscv-c.cc
+++ b/gcc/config/riscv/riscv-c.cc
@@ -194,8 +194,8 @@ riscv_pragma_intrinsic (cpp_reader *)
     {
       if (!TARGET_VECTOR)
    {
-     error ("%<#pragma riscv intrinsic%> option %qs needs 'V' extension "
-        "enabled",
+     error ("%<#pragma riscv intrinsic%> option %qs needs 'V' or "
+        "'XTHEADVECTOR' extension enabled",
         name);
      return;
    }
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index ecee7eb4727..754107cdaac 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -5323,7 +5323,7 @@ riscv_get_v_regno_alignment (machine_mode mode)
 static void
 riscv_print_operand (FILE *file, rtx op, int letter)
 {
-  /* `~` does not take an operand so op will be null
+  /* `~` and '^' does not take an operand so op will be null
      Check for before accessing op.
   */
   if (letter == '~')
@@ -5332,6 +5332,13 @@ riscv_print_operand (FILE *file, rtx op, int letter)
    fputc('w', file);
       return;
     }
+
+  if (letter == '^')
+    {
+      if (TARGET_XTHEADVECTOR)
+   fputs ("th.", file);
+      return;
+    }
   machine_mode mode = GET_MODE (op);
   enum rtx_code code = GET_CODE (op);

@@ -5584,7 +5591,7 @@ riscv_print_operand (FILE *file, rtx op, int letter)
 static bool
 riscv_print_operand_punct_valid_p (unsigned char code)
 {
-  return (code == '~');
+  return (code == '~' || code == '^');
 }

 /* Implement TARGET_PRINT_OPERAND_ADDRESS.  */
diff --git a/gcc/config/riscv/riscv_th_vector.h b/gcc/config/riscv/riscv_th_vector.h
new file mode 100644
index 00000000000..194652032bc
--- /dev/null
+++ b/gcc/config/riscv/riscv_th_vector.h
@@ -0,0 +1,49 @@
+/* RISC-V 'XTheadVector' Extension intrinsics include file.
+   Copyright (C) 2022-2023 Free Software Foundation, Inc.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+#ifndef __RISCV_TH_VECTOR_H
+#define __RISCV_TH_VECTOR_H
+
+#include <stdint.h>
+#include <stddef.h>
+
+#ifndef __riscv_xtheadvector
+#error "XTheadVector intrinsics require the xtheadvector extension."
+#else
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* NOTE: This implementation of riscv_vector.h is intentionally short.  It does
+   not define the RVV types and intrinsic functions directly in C and C++
+   code, but instead uses the following pragma to tell GCC to insert the
+   necessary type and function definitions itself.  The net effect is the
+   same, and the file is a complete implementation of riscv_vector.h.  */
+#pragma riscv intrinsic "vector"
+
+#ifdef __cplusplus
+}
+#endif // __cplusplus
+#endif // __riscv_xtheadvector
+#endif // __RISCV_TH_ECTOR_H
diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index f04c7fe5491..4b1ba84750c 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -3679,6 +3679,10 @@ (define_code_iterator any_int_binop [plus minus and ior xor ashift ashiftrt lshi

 (define_code_iterator any_int_unop [neg not])

+(define_code_iterator neg_unop [neg])
+
+(define_code_iterator not_unop [not])
+
 (define_code_iterator any_commutative_binop [plus and ior xor
   smax umax smin umin mult
 ])
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index d1499d330ff..2af237854f9 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -1099,9 +1099,9 @@ (define_insn "*mov<mode>_whole"
    (match_operand:V_WHOLE 1 "reg_or_mem_operand" "  m,vr,vr"))]
   "TARGET_VECTOR"
   "@
-   vl%m1re<sew>.v\t%0,%1
-   vs%m1r.v\t%1,%0
-   vmv%m1r.v\t%0,%1"
+   * return TARGET_XTHEADVECTOR ? \"th.vl%m1re.v\t%0,%1\" : \"vl%m1re<sew>.v\t%0,%1\";
+   %^vs%m1r.v\t%1,%0
+   %^vmv%m1r.v\t%0,%1"
   [(set_attr "type" "vldr,vstr,vmov")
    (set_attr "mode" "<MODE>")])

@@ -1109,7 +1109,7 @@ (define_insn "*mov<mode>_fract"
   [(set (match_operand:V_FRACT 0 "register_operand" "=vr")
    (match_operand:V_FRACT 1 "register_operand" " vr"))]
   "TARGET_VECTOR"
-  "vmv1r.v\t%0,%1"
+  "%^vmv1r.v\t%0,%1"
   [(set_attr "type" "vmov")
    (set_attr "mode" "<MODE>")])

@@ -1126,7 +1126,7 @@ (define_insn "*mov<mode>"
   [(set (match_operand:VB 0 "register_operand" "=vr")
    (match_operand:VB 1 "register_operand" " vr"))]
   "TARGET_VECTOR"
-  "vmv1r.v\t%0,%1"
+  "%^vmv1r.v\t%0,%1"
   [(set_attr "type" "vmov")
    (set_attr "mode" "<MODE>")])

@@ -1135,7 +1135,7 @@ (define_expand "@mov<V_FRACT:mode><P:mode>_lra"
     [(set (match_operand:V_FRACT 0 "reg_or_mem_operand")
      (match_operand:V_FRACT 1 "reg_or_mem_operand"))
    (clobber (match_scratch:P 2))])]
-  "TARGET_VECTOR && (lra_in_progress || reload_completed)"
+  "TARGET_VECTOR &&  (lra_in_progress || reload_completed)"
 {})

 (define_expand "@mov<VB:mode><P:mode>_lra"
@@ -1143,14 +1143,14 @@ (define_expand "@mov<VB:mode><P:mode>_lra"
     [(set (match_operand:VB 0 "reg_or_mem_operand")
      (match_operand:VB 1 "reg_or_mem_operand"))
    (clobber (match_scratch:P 2))])]
-  "TARGET_VECTOR && (lra_in_progress || reload_completed)"
+  "TARGET_VECTOR &&  (lra_in_progress || reload_completed)"
 {})

 (define_insn_and_split "*mov<V_FRACT:mode><P:mode>_lra"
   [(set (match_operand:V_FRACT 0 "reg_or_mem_operand" "=vr, m,vr")
    (match_operand:V_FRACT 1 "reg_or_mem_operand" "  m,vr,vr"))
    (clobber (match_scratch:P 2 "=&r,&r,X"))]
-  "TARGET_VECTOR && (lra_in_progress || reload_completed)"
+  "TARGET_VECTOR &&  (lra_in_progress || reload_completed)"
   "#"
   "&& reload_completed"
   [(const_int 0)]
@@ -1172,7 +1172,7 @@ (define_insn_and_split "*mov<VB:mode><P:mode>_lra"
   [(set (match_operand:VB 0 "reg_or_mem_operand" "=vr, m,vr")
    (match_operand:VB 1 "reg_or_mem_operand" "  m,vr,vr"))
    (clobber (match_scratch:P 2 "=&r,&r,X"))]
-  "TARGET_VECTOR && (lra_in_progress || reload_completed)"
+  "TARGET_VECTOR &&  (lra_in_progress || reload_completed)"
   "#"
   "&& reload_completed"
   [(const_int 0)]
@@ -1258,7 +1258,7 @@ (define_insn_and_split "*mov<mode>"
   "@
    #
    #
-   vmv%m1r.v\t%0,%1"
+   %^vmv%m1r.v\t%0,%1"
   "&& reload_completed
    && (!register_operand (operands[0], <MODE>mode)
        || !register_operand (operands[1], <MODE>mode))"
@@ -1286,14 +1286,14 @@ (define_expand "@mov<VLS_AVL_REG:mode><P:mode>_lra"
     [(set (match_operand:VLS_AVL_REG 0 "reg_or_mem_operand")
      (match_operand:VLS_AVL_REG 1 "reg_or_mem_operand"))
    (clobber (match_scratch:P 2))])]
-  "TARGET_VECTOR && (lra_in_progress || reload_completed)"
+  "TARGET_VECTOR &&  (lra_in_progress || reload_completed)"
 {})

 (define_insn_and_split "*mov<VLS_AVL_REG:mode><P:mode>_lra"
   [(set (match_operand:VLS_AVL_REG 0 "reg_or_mem_operand" "=vr, m,vr")
    (match_operand:VLS_AVL_REG 1 "reg_or_mem_operand" "  m,vr,vr"))
    (clobber (match_scratch:P 2 "=&r,&r,X"))]
-  "TARGET_VECTOR && (lra_in_progress || reload_completed)
+  "TARGET_VECTOR &&  (lra_in_progress || reload_completed)
    && (register_operand (operands[0], <VLS_AVL_REG:MODE>mode)
        || register_operand (operands[1], <VLS_AVL_REG:MODE>mode))"
   "#"
@@ -1322,7 +1322,7 @@ (define_insn "*mov<mode>_vls"
   [(set (match_operand:VLS 0 "register_operand" "=vr")
    (match_operand:VLS 1 "register_operand" " vr"))]
   "TARGET_VECTOR"
-  "vmv%m1r.v\t%0,%1"
+  "%^vmv%m1r.v\t%0,%1"
   [(set_attr "type" "vmov")
    (set_attr "mode" "<MODE>")])

@@ -1330,7 +1330,7 @@ (define_insn "*mov<mode>_vls"
   [(set (match_operand:VLSB 0 "register_operand" "=vr")
    (match_operand:VLSB 1 "register_operand" " vr"))]
   "TARGET_VECTOR"
-  "vmv1r.v\t%0,%1"
+  "%^vmv1r.v\t%0,%1"
   [(set_attr "type" "vmov")
    (set_attr "mode" "<MODE>")])

@@ -1359,7 +1359,7 @@ (define_expand "movmisalign<mode>"
 (define_expand "movmisalign<mode>"
   [(set (match_operand:V 0 "nonimmediate_operand")
    (match_operand:V 1 "general_operand"))]
-  "TARGET_VECTOR && TARGET_VECTOR_MISALIGN_SUPPORTED"
+  "TARGET_VECTOR &&  TARGET_VECTOR_MISALIGN_SUPPORTED"
   {
     emit_move_insn (operands[0], operands[1]);
     DONE;
@@ -1396,7 +1396,7 @@ (define_insn_and_split "*vec_duplicate<mode>"
   [(set (match_operand:V_VLS 0 "register_operand")
         (vec_duplicate:V_VLS
           (match_operand:<VEL> 1 "direct_broadcast_operand")))]
-  "TARGET_VECTOR && can_create_pseudo_p ()"
+  "TARGET_VECTOR &&  can_create_pseudo_p ()"
   "#"
   "&& 1"
   [(const_int 0)]
@@ -1530,7 +1530,7 @@ (define_insn "@vsetvl<mode>"
            (match_dup 4)
            (match_dup 5)] UNSPEC_VSETVL))]
   "TARGET_VECTOR"
-  "vset%i1vli\t%0,%1,e%2,%m3,t%p4,m%p5"
+  "%^vset%i1vli\t%0,%1,e%2,%m3,t%p4,m%p5"
   [(set_attr "type" "vsetvl")
    (set_attr "mode" "<MODE>")
    (set (attr "sew") (symbol_ref "INTVAL (operands[2])"))
@@ -1548,7 +1548,7 @@ (define_insn "vsetvl_vtype_change_only"
       (match_operand 2 "const_int_operand" "i")
       (match_operand 3 "const_int_operand" "i")] UNSPEC_VSETVL))]
   "TARGET_VECTOR"
-  "vsetvli\tzero,zero,e%0,%m1,t%p2,m%p3"
+  "%^vsetvli\tzero,zero,e%0,%m1,t%p2,m%p3"
   [(set_attr "type" "vsetvl")
    (set_attr "mode" "SI")
    (set (attr "sew") (symbol_ref "INTVAL (operands[0])"))
@@ -1570,7 +1570,7 @@ (define_insn "@vsetvl_discard_result<mode>"
            (match_operand 3 "const_int_operand" "i")
            (match_operand 4 "const_int_operand" "i")] UNSPEC_VSETVL))]
   "TARGET_VECTOR"
-  "vset%i0vli\tzero,%0,e%1,%m2,t%p3,m%p4"
+  "%^vset%i0vli\tzero,%0,e%1,%m2,t%p3,m%p4"
   [(set_attr "type" "vsetvl")
    (set_attr "mode" "<MODE>")
    (set (attr "sew") (symbol_ref "INTVAL (operands[1])"))
@@ -1720,12 +1720,12 @@ (define_insn_and_split "*pred_mov<mode>"
     && (register_operand (operands[0], <MODE>mode)
         || register_operand (operands[3], <MODE>mode)))"
   "@
-   vle<sew>.v\t%0,%3%p1
-   vle<sew>.v\t%0,%3
-   vle<sew>.v\t%0,%3,%1.t
-   vse<sew>.v\t%3,%0%p1
-   vmv.v.v\t%0,%3
-   vmv.v.v\t%0,%3"
+   * return TARGET_XTHEADVECTOR ? \"th.vle.v\t%0,%3%p1\" : \"vle<sew>.v\t%0,%3%p1\";
+   * return TARGET_XTHEADVECTOR ? \"th.vle.v\t%0,%3\" : \"vle<sew>.v\t%0,%3\";
+   * return TARGET_XTHEADVECTOR ? \"th.vle.v\t%0,%3,%1.t\" : \"vle<sew>.v\t%0,%3,%1.t\";
+   * return TARGET_XTHEADVECTOR ? \"th.vse.v\t%3,%0%p1\" : \"vse<sew>.v\t%3,%0%p1\";
+   %^vmv.v.v\t%0,%3
+   %^vmv.v.v\t%0,%3"
   "&& register_operand (operands[0], <MODE>mode)
    && register_operand (operands[3], <MODE>mode)
    && satisfies_constraint_vu (operands[2])
@@ -1749,7 +1749,7 @@ (define_insn "@pred_store<mode>"
      (match_operand:V 2 "register_operand"         "    vr")
      (match_dup 0)))]
   "TARGET_VECTOR"
-  "vse<sew>.v\t%2,%0%p1"
+  { return TARGET_XTHEADVECTOR ? "th.vse.v\t%2,%0%p1" : "vse<sew>.v\t%2,%0%p1"; }
   [(set_attr "type" "vste")
    (set_attr "mode" "<MODE>")
    (set (attr "avl_type_idx") (const_int 4))
@@ -1773,11 +1773,11 @@ (define_insn_and_split "@pred_mov<mode>"
      (match_operand:VB_VLS 2 "vector_undef_operand"             " vu,  vu,  vu,  vu,  vu")))]
   "TARGET_VECTOR"
   "@
-   vlm.v\t%0,%3
-   vsm.v\t%3,%0
-   vmmv.m\t%0,%3
-   vmclr.m\t%0
-   vmset.m\t%0"
+   %^vlm.v\t%0,%3
+   %^vsm.v\t%3,%0
+   %^vmmv.m\t%0,%3
+   %^vmclr.m\t%0
+   %^vmset.m\t%0"
   "&& register_operand (operands[0], <MODE>mode)
    && register_operand (operands[3], <MODE>mode)
    && INTVAL (operands[5]) == riscv_vector::VLMAX"
@@ -1800,7 +1800,7 @@ (define_insn "@pred_store<mode>"
      (match_operand:VB 2 "register_operand"                 " vr")
      (match_dup 0)))]
   "TARGET_VECTOR"
-  "vsm.v\t%2,%0"
+  "%^vsm.v\t%2,%0"
   [(set_attr "type" "vstm")
    (set_attr "mode" "<MODE>")
    (set (attr "avl_type_idx") (const_int 4))
@@ -1821,7 +1821,7 @@ (define_insn "@pred_merge<mode>"
    (match_operand:<VM> 4 "register_operand"     " vm,vm,vm,vm"))
       (match_operand:V_VLS 1 "vector_merge_operand"      " vu, 0,vu, 0")))]
   "TARGET_VECTOR"
-  "vmerge.v%o3m\t%0,%2,%v3,%4"
+  "%^vmerge.v%o3m\t%0,%2,%v3,%4"
   [(set_attr "type" "vimerge")
    (set_attr "mode" "<MODE>")])

@@ -1841,7 +1841,7 @@ (define_insn "@pred_merge<mode>_scalar"
    (match_operand:<VM> 4 "register_operand"     " vm,vm"))
       (match_operand:V_VLSI_QHS 1 "vector_merge_operand" " vu, 0")))]
   "TARGET_VECTOR"
-  "vmerge.vxm\t%0,%2,%3,%4"
+  "%^vmerge.vxm\t%0,%2,%3,%4"
   [(set_attr "type" "vimerge")
    (set_attr "mode" "<MODE>")])

@@ -1893,7 +1893,7 @@ (define_insn "*pred_merge<mode>_scalar"
    (match_operand:<VM> 4 "register_operand"     " vm,vm"))
       (match_operand:V_VLSI_D 1 "vector_merge_operand"   " vu, 0")))]
   "TARGET_VECTOR"
-  "vmerge.vxm\t%0,%2,%3,%4"
+  "%^vmerge.vxm\t%0,%2,%3,%4"
   [(set_attr "type" "vimerge")
    (set_attr "mode" "<MODE>")])

@@ -1914,7 +1914,7 @@ (define_insn "*pred_merge<mode>_extended_scalar"
    (match_operand:<VM> 4 "register_operand"         " vm,vm"))
       (match_operand:V_VLSI_D 1 "vector_merge_operand"       " vu, 0")))]
   "TARGET_VECTOR"
-  "vmerge.vxm\t%0,%2,%3,%4"
+  "%^vmerge.vxm\t%0,%2,%3,%4"
   [(set_attr "type" "vimerge")
    (set_attr "mode" "<MODE>")])

@@ -2004,14 +2004,14 @@ (define_insn_and_split "*pred_broadcast<mode>"
      (match_operand:V_VLSI 2 "vector_merge_operand"            "vu,  0, vu,  0, vu,  0, vu,  0")))]
   "TARGET_VECTOR"
   "@
-   vmv.v.x\t%0,%3
-   vmv.v.x\t%0,%3
-   vlse<sew>.v\t%0,%3,zero,%1.t
-   vlse<sew>.v\t%0,%3,zero,%1.t
-   vlse<sew>.v\t%0,%3,zero
-   vlse<sew>.v\t%0,%3,zero
-   vmv.s.x\t%0,%3
-   vmv.s.x\t%0,%3"
+   %^vmv.v.x\t%0,%3
+   %^vmv.v.x\t%0,%3
+   * return TARGET_XTHEADVECTOR ? \"th.vlse.v\t%0,%3,zero,%1.t\" : \"vlse<sew>.v\t%0,%3,zero,%1.t\";
+   * return TARGET_XTHEADVECTOR ? \"th.vlse.v\t%0,%3,zero,%1.t\" : \"vlse<sew>.v\t%0,%3,zero,%1.t\";
+   * return TARGET_XTHEADVECTOR ? \"th.vlse.v\t%0,%3,zero\" : \"vlse<sew>.v\t%0,%3,zero\";
+   * return TARGET_XTHEADVECTOR ? \"th.vlse.v\t%0,%3,zero\" : \"vlse<sew>.v\t%0,%3,zero\";
+   %^vmv.s.x\t%0,%3
+   %^vmv.s.x\t%0,%3"
   "(register_operand (operands[3], <VEL>mode)
   || CONST_POLY_INT_P (operands[3]))
   && GET_MODE_BITSIZE (<VEL>mode) > GET_MODE_BITSIZE (Pmode)"
@@ -2065,14 +2065,14 @@ (define_insn "*pred_broadcast<mode>"
      (match_operand:V_VLSF_ZVFHMIN 2 "vector_merge_operand"    "vu,  0, vu,  0, vu,  0, vu,  0")))]
   "TARGET_VECTOR"
   "@
-   vfmv.v.f\t%0,%3
-   vfmv.v.f\t%0,%3
-   vlse<sew>.v\t%0,%3,zero,%1.t
-   vlse<sew>.v\t%0,%3,zero,%1.t
-   vlse<sew>.v\t%0,%3,zero
-   vlse<sew>.v\t%0,%3,zero
-   vfmv.s.f\t%0,%3
-   vfmv.s.f\t%0,%3"
+   %^vfmv.v.f\t%0,%3
+   %^vfmv.v.f\t%0,%3
+   * return TARGET_XTHEADVECTOR ? \"th.vlse.v\t%0,%3,zero,%1.t\" : \"vlse<sew>.v\t%0,%3,zero,%1.t\";
+   * return TARGET_XTHEADVECTOR ? \"th.vlse.v\t%0,%3,zero,%1.t\" : \"vlse<sew>.v\t%0,%3,zero,%1.t\";
+   * return TARGET_XTHEADVECTOR ? \"th.vlse.v\t%0,%3,zero\" : \"vlse<sew>.v\t%0,%3,zero\";
+   * return TARGET_XTHEADVECTOR ? \"th.vlse.v\t%0,%3,zero\" : \"vlse<sew>.v\t%0,%3,zero\";
+   %^vfmv.s.f\t%0,%3
+   %^vfmv.s.f\t%0,%3"
   [(set_attr "type" "vfmov,vfmov,vlds,vlds,vlds,vlds,vfmovfv,vfmovfv")
    (set_attr "mode" "<MODE>")])

@@ -2093,10 +2093,10 @@ (define_insn "*pred_broadcast<mode>_extended_scalar"
      (match_operand:V_VLSI_D 2 "vector_merge_operand"          "vu,  0, vu,  0")))]
   "TARGET_VECTOR"
   "@
-   vmv.v.x\t%0,%3
-   vmv.v.x\t%0,%3
-   vmv.s.x\t%0,%3
-   vmv.s.x\t%0,%3"
+   %^vmv.v.x\t%0,%3
+   %^vmv.v.x\t%0,%3
+   %^vmv.s.x\t%0,%3
+   %^vmv.s.x\t%0,%3"
   [(set_attr "type" "vimov,vimov,vimovxv,vimovxv")
    (set_attr "mode" "<MODE>")])

@@ -2114,7 +2114,7 @@ (define_insn "*pred_broadcast<mode>_zero"
       (match_operand:V_VLS 3 "vector_const_0_operand"                      "Wc0,   Wc0")
       (match_operand:V_VLS 2 "vector_merge_operand"                        " vu,     0")))]
   "TARGET_VECTOR"
-  "vmv.s.x\t%0,zero"
+  "%^vmv.s.x\t%0,zero"
   [(set_attr "type" "vimovxv,vimovxv")
    (set_attr "mode" "<MODE>")])

@@ -2134,7 +2134,7 @@ (define_insn "*pred_broadcast<mode>_imm"
       (match_operand:V_VLS 3 "vector_const_int_or_double_0_operand" "viWc0, viWc0")
       (match_operand:V_VLS 2 "vector_merge_operand"                 "   vu,     0")))]
   "TARGET_VECTOR"
-  "vmv.v.i\t%0,%v3"
+  "%^vmv.v.i\t%0,%v3"
   [(set_attr "type" "vimov,vimov")
    (set_attr "mode" "<MODE>")])

@@ -2162,12 +2162,12 @@ (define_insn "@pred_strided_load<mode>"
      (match_operand:V 2 "vector_merge_operand"      "     0,    vu,    vu,    0,    vu,    vu")))]
   "TARGET_VECTOR"
   "@
-  vlse<sew>.v\t%0,%3,%z4%p1
-  vlse<sew>.v\t%0,%3,%z4
-  vlse<sew>.v\t%0,%3,%z4,%1.t
-  vle<sew>.v\t%0,%3%p1
-  vle<sew>.v\t%0,%3
-  vle<sew>.v\t%0,%3,%1.t"
+  * return TARGET_XTHEADVECTOR ? \"th.vlse.v\t%0,%3,%z4%p1\" : \"vlse<sew>.v\t%0,%3,%z4%p1\";
+  * return TARGET_XTHEADVECTOR ? \"th.vlse.v\t%0,%3,%z4\" : \"vlse<sew>.v\t%0,%3,%z4\";
+  * return TARGET_XTHEADVECTOR ? \"th.vlse.v\t%0,%3,%z4,%1.t\" : \"vlse<sew>.v\t%0,%3,%z4,%1.t\";
+  * return TARGET_XTHEADVECTOR ? \"th.vle.v\t%0,%3%p1\" : \"vle<sew>.v\t%0,%3%p1\";
+  * return TARGET_XTHEADVECTOR ? \"th.vle.v\t%0,%3\" : \"vle<sew>.v\t%0,%3\";
+  * return TARGET_XTHEADVECTOR ? \"th.vle.v\t%0,%3,%1.t\" : \"vle<sew>.v\t%0,%3,%1.t\";"
   [(set_attr "type" "vlds")
    (set_attr "mode" "<MODE>")])

@@ -2186,8 +2186,8 @@ (define_insn "@pred_strided_store<mode>"
      (match_dup 0)))]
   "TARGET_VECTOR"
   "@
-  vsse<sew>.v\t%3,%0,%z2%p1
-  vse<sew>.v\t%3,%0%p1"
+  * return TARGET_XTHEADVECTOR ? \"th.vsse.v\t%3,%0,%z2%p1\" : \"vsse<sew>.v\t%3,%0,%z2%p1\";
+  * return TARGET_XTHEADVECTOR ? \"th.vse.v\t%3,%0%p1\" : \"vse<sew>.v\t%3,%0%p1\";"
   [(set_attr "type" "vsts")
    (set_attr "mode" "<MODE>")
    (set (attr "avl_type_idx") (const_int 5))])
@@ -2217,7 +2217,7 @@ (define_insn "@pred_indexed_<order>load<mode>_same_eew"
         (match_operand:<VINDEX> 4 "register_operand" " vr, vr,vr, vr")] ORDER)
      (match_operand:V 2 "vector_merge_operand"       " vu, vu, 0,  0")))]
   "TARGET_VECTOR"
-  "vl<order>xei<sew>.v\t%0,(%z3),%4%p1"
+  { return TARGET_XTHEADVECTOR ? "th.vlxe.v\t%0,(%z3),%4%p1" : "vl<order>xei<sew>.v\t%0,(%z3),%4%p1"; }
   [(set_attr "type" "vld<order>x")
    (set_attr "mode" "<MODE>")])

@@ -2498,18 +2498,18 @@ (define_insn "@pred_<optab><mode>"
      (match_operand:V_VLSI 2 "vector_merge_operand"     "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0")))]
   "TARGET_VECTOR"
   "@
-   v<insn>.vv\t%0,%3,%4%p1
-   v<insn>.vv\t%0,%3,%4%p1
-   v<insn>.vv\t%0,%3,%4%p1
-   v<insn>.vv\t%0,%3,%4%p1
-   v<binop_vi_variant_insn>\t%0,<binop_vi_variant_op>%p1
-   v<binop_vi_variant_insn>\t%0,<binop_vi_variant_op>%p1
-   v<binop_vi_variant_insn>\t%0,<binop_vi_variant_op>%p1
-   v<binop_vi_variant_insn>\t%0,<binop_vi_variant_op>%p1
-   v<binop_reverse_vi_variant_insn>\t%0,<binop_reverse_vi_variant_op>%p1
-   v<binop_reverse_vi_variant_insn>\t%0,<binop_reverse_vi_variant_op>%p1
-   v<binop_reverse_vi_variant_insn>\t%0,<binop_reverse_vi_variant_op>%p1
-   v<binop_reverse_vi_variant_insn>\t%0,<binop_reverse_vi_variant_op>%p1"
+   %^v<insn>.vv\t%0,%3,%4%p1
+   %^v<insn>.vv\t%0,%3,%4%p1
+   %^v<insn>.vv\t%0,%3,%4%p1
+   %^v<insn>.vv\t%0,%3,%4%p1
+   %^v<binop_vi_variant_insn>\t%0,<binop_vi_variant_op>%p1
+   %^v<binop_vi_variant_insn>\t%0,<binop_vi_variant_op>%p1
+   %^v<binop_vi_variant_insn>\t%0,<binop_vi_variant_op>%p1
+   %^v<binop_vi_variant_insn>\t%0,<binop_vi_variant_op>%p1
+   %^v<binop_reverse_vi_variant_insn>\t%0,<binop_reverse_vi_variant_op>%p1
+   %^v<binop_reverse_vi_variant_insn>\t%0,<binop_reverse_vi_variant_op>%p1
+   %^v<binop_reverse_vi_variant_insn>\t%0,<binop_reverse_vi_variant_op>%p1
+   %^v<binop_reverse_vi_variant_insn>\t%0,<binop_reverse_vi_variant_op>%p1"
   [(set_attr "type" "<int_binop_insn_type>")
    (set_attr "mode" "<MODE>")])

@@ -2533,7 +2533,7 @@ (define_insn "@pred_<optab><mode>_scalar"
        (match_operand 4 "pmode_reg_or_uimm5_operand" " r, r,  r,  r, K, K,  K,  K"))
      (match_operand:V_VLSI 2 "vector_merge_operand"      "vu, 0, vu,  0,vu, 0, vu,  0")))]
   "TARGET_VECTOR"
-  "v<insn>.v%o4\t%0,%3,%4%p1"
+  "%^v<insn>.v%o4\t%0,%3,%4%p1"
   [(set_attr "type" "vshift")
    (set_attr "mode" "<MODE>")])

@@ -2555,7 +2555,7 @@ (define_insn "@pred_<optab><mode>_scalar"
        (match_operand:V_VLSI_QHS 3 "register_operand"   "vr,vr, vr, vr"))
      (match_operand:V_VLSI_QHS 2 "vector_merge_operand" "vu, 0, vu,  0")))]
   "TARGET_VECTOR"
-  "v<insn>.vx\t%0,%3,%z4%p1"
+  "%^v<insn>.vx\t%0,%3,%z4%p1"
   [(set_attr "type" "<int_binop_insn_type>")
    (set_attr "mode" "<MODE>")])

@@ -2576,7 +2576,7 @@ (define_insn "@pred_<optab><mode>_scalar"
          (match_operand:<VEL> 4 "reg_or_0_operand"  "rJ,rJ, rJ, rJ")))
      (match_operand:V_VLSI_QHS 2 "vector_merge_operand" "vu, 0, vu,  0")))]
   "TARGET_VECTOR"
-  "v<insn>.vx\t%0,%3,%z4%p1"
+  "%^v<insn>.vx\t%0,%3,%z4%p1"
   [(set_attr "type" "<int_binop_insn_type>")
    (set_attr "mode" "<MODE>")])

@@ -2597,7 +2597,7 @@ (define_insn "@pred_sub<mode>_reverse_scalar"
        (match_operand:V_VLSI_QHS 3 "register_operand"   "vr,vr, vr, vr"))
      (match_operand:V_VLSI_QHS 2 "vector_merge_operand" "vu, 0, vu,  0")))]
   "TARGET_VECTOR"
-  "vrsub.vx\t%0,%3,%z4%p1"
+  "%^vrsub.vx\t%0,%3,%z4%p1"
   [(set_attr "type" "vialu")
    (set_attr "mode" "<MODE>")])

@@ -2653,7 +2653,7 @@ (define_insn "*pred_<optab><mode>_scalar"
        (match_operand:V_VLSI_D 3 "register_operand"     "vr,vr, vr, vr"))
      (match_operand:V_VLSI_D 2 "vector_merge_operand"   "vu, 0, vu,  0")))]
   "TARGET_VECTOR"
-  "v<insn>.vx\t%0,%3,%z4%p1"
+  "%^v<insn>.vx\t%0,%3,%z4%p1"
   [(set_attr "type" "<int_binop_insn_type>")
    (set_attr "mode" "<MODE>")])

@@ -2675,7 +2675,7 @@ (define_insn "*pred_<optab><mode>_extended_scalar"
        (match_operand:V_VLSI_D 3 "register_operand"         "vr,vr, vr, vr"))
      (match_operand:V_VLSI_D 2 "vector_merge_operand"       "vu, 0, vu,  0")))]
   "TARGET_VECTOR"
-  "v<insn>.vx\t%0,%3,%z4%p1"
+  "%^v<insn>.vx\t%0,%3,%z4%p1"
   [(set_attr "type" "<int_binop_insn_type>")
    (set_attr "mode" "<MODE>")])

@@ -2729,7 +2729,7 @@ (define_insn "*pred_<optab><mode>_scalar"
          (match_operand:<VEL> 4 "reg_or_0_operand"  "rJ,rJ, rJ, rJ")))
      (match_operand:V_VLSI_D 2 "vector_merge_operand"   "vu, 0, vu,  0")))]
   "TARGET_VECTOR"
-  "v<insn>.vx\t%0,%3,%z4%p1"
+  "%^v<insn>.vx\t%0,%3,%z4%p1"
   [(set_attr "type" "<int_binop_insn_type>")
    (set_attr "mode" "<MODE>")])

@@ -2751,7 +2751,7 @@ (define_insn "*pred_<optab><mode>_extended_scalar"
            (match_operand:<VSUBEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ"))))
      (match_operand:V_VLSI_D 2 "vector_merge_operand"       "vu, 0, vu,  0")))]
   "TARGET_VECTOR"
-  "v<insn>.vx\t%0,%3,%z4%p1"
+  "%^v<insn>.vx\t%0,%3,%z4%p1"
   [(set_attr "type" "<int_binop_insn_type>")
    (set_attr "mode" "<MODE>")])

@@ -2805,7 +2805,7 @@ (define_insn "*pred_sub<mode>_reverse_scalar"
        (match_operand:V_VLSI_D 3 "register_operand"     "vr,vr, vr, vr"))
      (match_operand:V_VLSI_D 2 "vector_merge_operand"   "vu, 0, vu,  0")))]
   "TARGET_VECTOR"
-  "vrsub.vx\t%0,%3,%z4%p1"
+  "%^vrsub.vx\t%0,%3,%z4%p1"
   [(set_attr "type" "vialu")
    (set_attr "mode" "<MODE>")])

@@ -2827,7 +2827,7 @@ (define_insn "*pred_sub<mode>_extended_reverse_scalar"
        (match_operand:V_VLSI_D 3 "register_operand"         "vr,vr, vr, vr"))
      (match_operand:V_VLSI_D 2 "vector_merge_operand"       "vu, 0, vu,  0")))]
   "TARGET_VECTOR"
-  "vrsub.vx\t%0,%3,%z4%p1"
+  "%^vrsub.vx\t%0,%3,%z4%p1"
   [(set_attr "type" "vialu")
    (set_attr "mode" "<MODE>")])

@@ -2848,7 +2848,7 @@ (define_insn "@pred_mulh<v_su><mode>"
         (match_operand:VFULLI 4 "register_operand"  "vr,vr, vr, vr")] VMULH)
      (match_operand:VFULLI 2 "vector_merge_operand" "vu, 0, vu,  0")))]
   "TARGET_VECTOR"
-  "vmulh<v_su>.vv\t%0,%3,%4%p1"
+  "%^vmulh<v_su>.vv\t%0,%3,%4%p1"
   [(set_attr "type" "vimul")
    (set_attr "mode" "<MODE>")])

@@ -2869,7 +2869,7 @@ (define_insn "@pred_mulh<v_su><mode>_scalar"
         (match_operand:VI_QHS 3 "register_operand"   "vr,vr, vr, vr")] VMULH)
      (match_operand:VI_QHS 2 "vector_merge_operand"  "vu, 0, vu,  0")))]
   "TARGET_VECTOR"
-  "vmulh<v_su>.vx\t%0,%3,%z4%p1"
+  "%^vmulh<v_su>.vx\t%0,%3,%z4%p1"
   [(set_attr "type" "vimul")
    (set_attr "mode" "<MODE>")])

@@ -2923,7 +2923,7 @@ (define_insn "*pred_mulh<v_su><mode>_scalar"
         (match_operand:VFULLI_D 3 "register_operand"  "vr,vr, vr, vr")] VMULH)
      (match_operand:VFULLI_D 2 "vector_merge_operand" "vu, 0, vu,  0")))]
   "TARGET_VECTOR"
-  "vmulh<v_su>.vx\t%0,%3,%z4%p1"
+  "%^vmulh<v_su>.vx\t%0,%3,%z4%p1"
   [(set_attr "type" "vimul")
    (set_attr "mode" "<MODE>")])

@@ -2945,7 +2945,7 @@ (define_insn "*pred_mulh<v_su><mode>_extended_scalar"
         (match_operand:VFULLI_D 3 "register_operand"     "vr,vr, vr, vr")] VMULH)
      (match_operand:VFULLI_D 2 "vector_merge_operand"    "vu, 0, vu,  0")))]
   "TARGET_VECTOR"
-  "vmulh<v_su>.vx\t%0,%3,%z4%p1"
+  "%^vmulh<v_su>.vx\t%0,%3,%z4%p1"
   [(set_attr "type" "vimul")
    (set_attr "mode" "<MODE>")])

@@ -2966,7 +2966,7 @@ (define_insn "@pred_adc<mode>"
         (match_operand:<VM> 4 "register_operand"     "vm,vm,vm,vm")] UNSPEC_VADC)
      (match_operand:VI 1 "vector_merge_operand"      "vu, 0,vu, 0")))]
   "TARGET_VECTOR"
-  "vadc.v%o3m\t%0,%2,%v3,%4"
+  "%^vadc.v%o3m\t%0,%2,%v3,%4"
   [(set_attr "type" "vicalu")
    (set_attr "mode" "<MODE>")
    (set_attr "merge_op_idx" "1")
@@ -2990,7 +2990,7 @@ (define_insn "@pred_sbc<mode>"
          (match_operand:<VM> 4 "register_operand"    "vm,vm")] UNSPEC_VSBC)
      (match_operand:VI 1 "vector_merge_operand"      "vu, 0")))]
   "TARGET_VECTOR"
-  "vsbc.vvm\t%0,%2,%3,%4"
+  "%^vsbc.vvm\t%0,%2,%3,%4"
   [(set_attr "type" "vicalu")
    (set_attr "mode" "<MODE>")
    (set_attr "merge_op_idx" "1")
@@ -3015,7 +3015,7 @@ (define_insn "@pred_adc<mode>_scalar"
         (match_operand:<VM> 4 "register_operand"      "vm,vm")] UNSPEC_VADC)
      (match_operand:VI_QHS 1 "vector_merge_operand"   "vu, 0")))]
   "TARGET_VECTOR"
-  "vadc.vxm\t%0,%2,%3,%4"
+  "%^vadc.vxm\t%0,%2,%3,%4"
   [(set_attr "type" "vicalu")
    (set_attr "mode" "<MODE>")
    (set_attr "merge_op_idx" "1")
@@ -3040,7 +3040,7 @@ (define_insn "@pred_sbc<mode>_scalar"
          (match_operand:<VM> 4 "register_operand"      "vm,vm")] UNSPEC_VSBC)
      (match_operand:VI_QHS 1 "vector_merge_operand"    "vu, 0")))]
   "TARGET_VECTOR"
-  "vsbc.vxm\t%0,%2,%z3,%4"
+  "%^vsbc.vxm\t%0,%2,%z3,%4"
   [(set_attr "type" "vicalu")
    (set_attr "mode" "<MODE>")
    (set_attr "merge_op_idx" "1")
@@ -3098,7 +3098,7 @@ (define_insn "*pred_adc<mode>_scalar"
          (match_operand:<VM> 4 "register_operand"      "vm,vm")] UNSPEC_VADC)
      (match_operand:VI_D 1 "vector_merge_operand"      "vu, 0")))]
   "TARGET_VECTOR"
-  "vadc.vxm\t%0,%2,%z3,%4"
+  "%^vadc.vxm\t%0,%2,%z3,%4"
   [(set_attr "type" "vicalu")
    (set_attr "mode" "<MODE>")
    (set_attr "merge_op_idx" "1")
@@ -3124,7 +3124,7 @@ (define_insn "*pred_adc<mode>_extended_scalar"
          (match_operand:<VM> 4 "register_operand"           "vm,vm")] UNSPEC_VADC)
      (match_operand:VI_D 1 "vector_merge_operand"           "vu, 0")))]
   "TARGET_VECTOR"
-  "vadc.vxm\t%0,%2,%z3,%4"
+  "%^vadc.vxm\t%0,%2,%z3,%4"
   [(set_attr "type" "vicalu")
    (set_attr "mode" "<MODE>")
    (set_attr "merge_op_idx" "1")
@@ -3182,7 +3182,7 @@ (define_insn "*pred_sbc<mode>_scalar"
          (match_operand:<VM> 4 "register_operand"      "vm,vm")] UNSPEC_VSBC)
      (match_operand:VI_D 1 "vector_merge_operand"      "vu, 0")))]
   "TARGET_VECTOR"
-  "vsbc.vxm\t%0,%2,%z3,%4"
+  "%^vsbc.vxm\t%0,%2,%z3,%4"
   [(set_attr "type" "vicalu")
    (set_attr "mode" "<MODE>")
    (set_attr "merge_op_idx" "1")
@@ -3208,7 +3208,7 @@ (define_insn "*pred_sbc<mode>_extended_scalar"
          (match_operand:<VM> 4 "register_operand"           "vm,vm")] UNSPEC_VSBC)
      (match_operand:VI_D 1 "vector_merge_operand"           "vu, 0")))]
   "TARGET_VECTOR"
-  "vsbc.vxm\t%0,%2,%z3,%4"
+  "%^vsbc.vxm\t%0,%2,%z3,%4"
   [(set_attr "type" "vicalu")
    (set_attr "mode" "<MODE>")
    (set_attr "merge_op_idx" "1")
@@ -3229,7 +3229,7 @@ (define_insn "@pred_madc<mode>"
           (reg:SI VL_REGNUM)
           (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMADC))]
   "TARGET_VECTOR"
-  "vmadc.v%o2m\t%0,%1,%v2,%3"
+  "%^vmadc.v%o2m\t%0,%1,%v2,%3"
   [(set_attr "type" "vicalu")
    (set_attr "mode" "<MODE>")
    (set_attr "vl_op_idx" "4")
@@ -3248,7 +3248,7 @@ (define_insn "@pred_msbc<mode>"
           (reg:SI VL_REGNUM)
           (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMSBC))]
   "TARGET_VECTOR"
-  "vmsbc.vvm\t%0,%1,%2,%3"
+  "%^vmsbc.vvm\t%0,%1,%2,%3"
   [(set_attr "type" "vicalu")
    (set_attr "mode" "<MODE>")
    (set_attr "vl_op_idx" "4")
@@ -3268,7 +3268,7 @@ (define_insn "@pred_madc<mode>_scalar"
           (reg:SI VL_REGNUM)
           (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMADC))]
   "TARGET_VECTOR"
-  "vmadc.vxm\t%0,%1,%2,%3"
+  "%^vmadc.vxm\t%0,%1,%2,%3"
   [(set_attr "type" "vicalu")
    (set_attr "mode" "<MODE>")
    (set_attr "vl_op_idx" "4")
@@ -3288,7 +3288,7 @@ (define_insn "@pred_msbc<mode>_scalar"
           (reg:SI VL_REGNUM)
           (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMSBC))]
   "TARGET_VECTOR"
-  "vmsbc.vxm\t%0,%1,%z2,%3"
+  "%^vmsbc.vxm\t%0,%1,%z2,%3"
   [(set_attr "type" "vicalu")
    (set_attr "mode" "<MODE>")
    (set_attr "vl_op_idx" "4")
@@ -3337,7 +3337,7 @@ (define_insn "*pred_madc<mode>_scalar"
           (reg:SI VL_REGNUM)
           (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMADC))]
   "TARGET_VECTOR"
-  "vmadc.vxm\t%0,%1,%z2,%3"
+  "%^vmadc.vxm\t%0,%1,%z2,%3"
   [(set_attr "type" "vicalu")
    (set_attr "mode" "<MODE>")
    (set_attr "vl_op_idx" "4")
@@ -3358,7 +3358,7 @@ (define_insn "*pred_madc<mode>_extended_scalar"
           (reg:SI VL_REGNUM)
           (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMADC))]
   "TARGET_VECTOR"
-  "vmadc.vxm\t%0,%1,%z2,%3"
+  "%^vmadc.vxm\t%0,%1,%z2,%3"
   [(set_attr "type" "vicalu")
    (set_attr "mode" "<MODE>")
    (set_attr "vl_op_idx" "4")
@@ -3407,7 +3407,7 @@ (define_insn "*pred_msbc<mode>_scalar"
           (reg:SI VL_REGNUM)
           (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMSBC))]
   "TARGET_VECTOR"
-  "vmsbc.vxm\t%0,%1,%z2,%3"
+  "%^vmsbc.vxm\t%0,%1,%z2,%3"
   [(set_attr "type" "vicalu")
    (set_attr "mode" "<MODE>")
    (set_attr "vl_op_idx" "4")
@@ -3428,7 +3428,7 @@ (define_insn "*pred_msbc<mode>_extended_scalar"
           (reg:SI VL_REGNUM)
           (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMSBC))]
   "TARGET_VECTOR"
-  "vmsbc.vxm\t%0,%1,%z2,%3"
+  "%^vmsbc.vxm\t%0,%1,%z2,%3"
   [(set_attr "type" "vicalu")
    (set_attr "mode" "<MODE>")
    (set_attr "vl_op_idx" "4")
@@ -3446,7 +3446,7 @@ (define_insn "@pred_madc<mode>_overflow"
           (reg:SI VL_REGNUM)
           (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
   "TARGET_VECTOR"
-  "vmadc.v%o2\t%0,%1,%v2"
+  "%^vmadc.v%o2\t%0,%1,%v2"
   [(set_attr "type" "vicalu")
    (set_attr "mode" "<MODE>")
    (set_attr "vl_op_idx" "3")
@@ -3464,7 +3464,7 @@ (define_insn "@pred_msbc<mode>_overflow"
           (reg:SI VL_REGNUM)
           (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
   "TARGET_VECTOR"
-  "vmsbc.vv\t%0,%1,%2"
+  "%^vmsbc.vv\t%0,%1,%2"
   [(set_attr "type" "vicalu")
    (set_attr "mode" "<MODE>")
    (set_attr "vl_op_idx" "3")
@@ -3483,7 +3483,7 @@ (define_insn "@pred_madc<mode>_overflow_scalar"
           (reg:SI VL_REGNUM)
           (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
   "TARGET_VECTOR"
-  "vmadc.vx\t%0,%1,%z2"
+  "%^vmadc.vx\t%0,%1,%z2"
   [(set_attr "type" "vicalu")
    (set_attr "mode" "<MODE>")
    (set_attr "vl_op_idx" "3")
@@ -3502,7 +3502,7 @@ (define_insn "@pred_msbc<mode>_overflow_scalar"
           (reg:SI VL_REGNUM)
           (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
   "TARGET_VECTOR"
-  "vmsbc.vx\t%0,%1,%z2"
+  "%^vmsbc.vx\t%0,%1,%z2"
   [(set_attr "type" "vicalu")
    (set_attr "mode" "<MODE>")
    (set_attr "vl_op_idx" "3")
@@ -3549,7 +3549,7 @@ (define_insn "*pred_madc<mode>_overflow_scalar"
           (reg:SI VL_REGNUM)
           (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
   "TARGET_VECTOR"
-  "vmadc.vx\t%0,%1,%z2"
+  "%^vmadc.vx\t%0,%1,%z2"
   [(set_attr "type" "vicalu")
    (set_attr "mode" "<MODE>")
    (set_attr "vl_op_idx" "3")
@@ -3569,7 +3569,7 @@ (define_insn "*pred_madc<mode>_overflow_extended_scalar"
           (reg:SI VL_REGNUM)
           (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
   "TARGET_VECTOR"
-  "vmadc.vx\t%0,%1,%z2"
+  "%^vmadc.vx\t%0,%1,%z2"
   [(set_attr "type" "vicalu")
    (set_attr "mode" "<MODE>")
    (set_attr "vl_op_idx" "3")
@@ -3616,7 +3616,7 @@ (define_insn "*pred_msbc<mode>_overflow_scalar"
           (reg:SI VL_REGNUM)
           (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
   "TARGET_VECTOR"
-  "vmsbc.vx\t%0,%1,%z2"
+  "%^vmsbc.vx\t%0,%1,%z2"
   [(set_attr "type" "vicalu")
    (set_attr "mode" "<MODE>")
    (set_attr "vl_op_idx" "3")
@@ -3636,7 +3636,7 @@ (define_insn "*pred_msbc<mode>_overflow_extended_scalar"
           (reg:SI VL_REGNUM)
           (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
   "TARGET_VECTOR"
-  "vmsbc.vx\t%0,%1,%z2"
+  "%^vmsbc.vx\t%0,%1,%z2"
   [(set_attr "type" "vicalu")
    (set_attr "mode" "<MODE>")
    (set_attr "vl_op_idx" "3")
@@ -3660,11 +3660,34 @@ (define_insn "@pred_<optab><mode>"
         (match_operand 7 "const_int_operand"        " i, i,  i,  i")
         (reg:SI VL_REGNUM)
         (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-     (any_int_unop:V_VLSI
+     (not_unop:V_VLSI
        (match_operand:V_VLSI 3 "register_operand"       "vr,vr, vr, vr"))
      (match_operand:V_VLSI 2 "vector_merge_operand"     "vu, 0, vu,  0")))]
   "TARGET_VECTOR"
-  "v<insn>.v\t%0,%3%p1"
+  "%^vnot.v\t%0,%3%p1"
+  [(set_attr "type" "vialu")
+   (set_attr "mode" "<MODE>")
+   (set_attr "vl_op_idx" "4")
+   (set (attr "ta") (symbol_ref "riscv_vector::get_ta (operands[5])"))
+   (set (attr "ma") (symbol_ref "riscv_vector::get_ma (operands[6])"))
+   (set (attr "avl_type_idx") (const_int 7))])
+
+(define_insn "@pred_<optab><mode>"
+  [(set (match_operand:V_VLSI 0 "register_operand"  "=vd,vd, vr, vr")
+   (if_then_else:V_VLSI
+     (unspec:<VM>
+       [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
+        (match_operand 4 "vector_length_operand"    "rK,rK, rK, rK")
+        (match_operand 5 "const_int_operand"    " i, i,  i,  i")
+        (match_operand 6 "const_int_operand"    " i, i,  i,  i")
+        (match_operand 7 "const_int_operand"    " i, i,  i,  i")
+        (reg:SI VL_REGNUM)
+        (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+     (neg_unop:V_VLSI
+       (match_operand:V_VLSI 3 "register_operand"       "vr,vr, vr, vr"))
+     (match_operand:V_VLSI 2 "vector_merge_operand"     "vu, 0, vu,  0")))]
+  "TARGET_VECTOR"
+  { return TARGET_XTHEADVECTOR ? "th.vrsub.vx\t%0,%3,x0%p1" : "vneg.v\t%0,%3%p1"; }
   [(set_attr "type" "vialu")
    (set_attr "mode" "<MODE>")
    (set_attr "vl_op_idx" "4")
@@ -3696,7 +3719,7 @@ (define_insn "@pred_<optab><mode>_vf2"
      (any_extend:VWEXTI
        (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" "   vr,   vr"))
      (match_operand:VWEXTI 2 "vector_merge_operand"         "   vu,    0")))]
-  "TARGET_VECTOR"
+  "TARGET_VECTOR && !TARGET_XTHEADVECTOR"
   "v<sz>ext.vf2\t%0,%3%p1"
   [(set_attr "type" "vext")
    (set_attr "mode" "<MODE>")])
@@ -3716,7 +3739,7 @@ (define_insn "@pred_<optab><mode>_vf4"
      (any_extend:VQEXTI
        (match_operand:<V_QUAD_TRUNC> 3 "register_operand" "   vr,   vr"))
      (match_operand:VQEXTI 2 "vector_merge_operand"       "   vu,    0")))]
-  "TARGET_VECTOR"
+  "TARGET_VECTOR && !TARGET_XTHEADVECTOR"
   "v<sz>ext.vf4\t%0,%3%p1"
   [(set_attr "type" "vext")
    (set_attr "mode" "<MODE>")])
@@ -3736,7 +3759,7 @@ (define_insn "@pred_<optab><mode>_vf8"
      (any_extend:VOEXTI
        (match_operand:<V_OCT_TRUNC> 3 "register_operand" "   vr,   vr"))
      (match_operand:VOEXTI 2 "vector_merge_operand"      "   vu,    0")))]
-  "TARGET_VECTOR"
+  "TARGET_VECTOR && !TARGET_XTHEADVECTOR"
   "v<sz>ext.vf8\t%0,%3%p1"
   [(set_attr "type" "vext")
    (set_attr "mode" "<MODE>")])
@@ -3760,7 +3783,7 @@ (define_insn "@pred_dual_widen_<any_widen_binop:optab><any_extend:su><mode>"
          (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" "   vr,   vr")))
      (match_operand:VWEXTI 2 "vector_merge_operand"           "   vu,    0")))]
   "TARGET_VECTOR"
-  "vw<any_widen_binop:insn><any_extend:u>.vv\t%0,%3,%4%p1"
+  "%^vw<any_widen_binop:insn><any_extend:u>.vv\t%0,%3,%4%p1"
   [(set_attr "type" "vi<widen_binop_insn_type>")
    (set_attr "mode" "<V_DOUBLE_TRUNC>")])

@@ -3783,7 +3806,7 @@ (define_insn "@pred_dual_widen_<any_widen_binop:optab><any_extend:su><mode>_scal
        (match_operand:<VSUBEL> 4 "reg_or_0_operand"       "   rJ,   rJ"))))
      (match_operand:VWEXTI 2 "vector_merge_operand"           "   vu,    0")))]
   "TARGET_VECTOR"
-  "vw<any_widen_binop:insn><any_extend:u>.vx\t%0,%3,%z4%p1"
+  "%^vw<any_widen_binop:insn><any_extend:u>.vx\t%0,%3,%z4%p1"
   [(set_attr "type" "vi<widen_binop_insn_type>")
    (set_attr "mode" "<V_DOUBLE_TRUNC>")])

@@ -3804,7 +3827,7 @@ (define_insn "@pred_single_widen_sub<any_extend:su><mode>"
          (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" "   vr,   vr")))
      (match_operand:VWEXTI 2 "vector_merge_operand"           "   vu,    0")))]
   "TARGET_VECTOR"
-  "vwsub<any_extend:u>.wv\t%0,%3,%4%p1"
+  "%^vwsub<any_extend:u>.wv\t%0,%3,%4%p1"
   [(set_attr "type" "viwalu")
    (set_attr "mode" "<V_DOUBLE_TRUNC>")])

@@ -3825,7 +3848,7 @@ (define_insn "@pred_single_widen_add<any_extend:su><mode>"
        (match_operand:VWEXTI 3 "register_operand"             "   vr,   vr"))
      (match_operand:VWEXTI 2 "vector_merge_operand"           "   vu,    0")))]
   "TARGET_VECTOR"
-  "vwadd<any_extend:u>.wv\t%0,%3,%4%p1"
+  "%^vwadd<any_extend:u>.wv\t%0,%3,%4%p1"
   [(set_attr "type" "viwalu")
    (set_attr "mode" "<V_DOUBLE_TRUNC>")])

@@ -3847,7 +3870,7 @@ (define_insn "@pred_single_widen_<plus_minus:optab><any_extend:su><mode>_scalar"
        (match_operand:<VSUBEL> 4 "reg_or_0_operand"       "   rJ,   rJ"))))
      (match_operand:VWEXTI 2 "vector_merge_operand"           "   vu,    0")))]
   "TARGET_VECTOR"
-  "vw<plus_minus:insn><any_extend:u>.wx\t%0,%3,%z4%p1"
+  "%^vw<plus_minus:insn><any_extend:u>.wx\t%0,%3,%z4%p1"
   [(set_attr "type" "vi<widen_binop_insn_type>")
    (set_attr "mode" "<V_DOUBLE_TRUNC>")])

@@ -3869,7 +3892,7 @@ (define_insn "@pred_widen_mulsu<mode>"
          (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" "   vr,   vr")))
      (match_operand:VWEXTI 2 "vector_merge_operand"           "   vu,    0")))]
   "TARGET_VECTOR"
-  "vwmulsu.vv\t%0,%3,%4%p1"
+  "%^vwmulsu.vv\t%0,%3,%4%p1"
   [(set_attr "type" "viwmul")
    (set_attr "mode" "<V_DOUBLE_TRUNC>")])

@@ -3892,7 +3915,7 @@ (define_insn "@pred_widen_mulsu<mode>_scalar"
        (match_operand:<VSUBEL> 4 "reg_or_0_operand"       "   rJ,   rJ"))))
      (match_operand:VWEXTI 2 "vector_merge_operand"           "   vu,    0")))]
   "TARGET_VECTOR"
-  "vwmulsu.vx\t%0,%3,%z4%p1"
+  "%^vwmulsu.vx\t%0,%3,%z4%p1"
   [(set_attr "type" "viwmul")
    (set_attr "mode" "<V_DOUBLE_TRUNC>")])

@@ -3915,7 +3938,7 @@ (define_insn "@pred_<optab><mode>"
          (reg:<VEL> X0_REGNUM)))
      (match_operand:VWEXTI 2 "vector_merge_operand"           "   vu,    0")))]
   "TARGET_VECTOR"
-  "vwcvt<u>.x.x.v\t%0,%3%p1"
+  "%^vwcvt<u>.x.x.v\t%0,%3%p1"
   [(set_attr "type" "viwalu")
    (set_attr "mode" "<V_DOUBLE_TRUNC>")
    (set_attr "vl_op_idx" "4")
@@ -3950,7 +3973,7 @@ (define_insn "@pred_narrow_<optab><mode>"
         (match_operand:<V_DOUBLE_TRUNC> 4 "vector_shift_operand"  "  0, 0,  0,  0,vr, vr,   vr,   vr, vk, vk,   vk,   vk")))
      (match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand"     "  0,vu,  0, vu,vu, vu,   vu,    0, vu, vu,   vu,    0")))]
   "TARGET_VECTOR"
-  "vn<insn>.w%o4\t%0,%3,%v4%p1"
+  "%^vn<insn>.w%o4\t%0,%3,%v4%p1"
   [(set_attr "type" "vnshift")
    (set_attr "mode" "<V_DOUBLE_TRUNC>")])

@@ -3971,7 +3994,7 @@ (define_insn "@pred_narrow_<optab><mode>_scalar"
         (match_operand 4 "pmode_reg_or_uimm5_operand"             " rK, rK, rK, rK,   rK,   rK")))
      (match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand"     " vu,  0, vu,  0,   vu,    0")))]
   "TARGET_VECTOR"
-  "vn<insn>.w%o4\t%0,%3,%4%p1"
+  "%^vn<insn>.w%o4\t%0,%3,%4%p1"
   [(set_attr "type" "vnshift")
    (set_attr "mode" "<V_DOUBLE_TRUNC>")])

@@ -3991,7 +4014,7 @@ (define_insn "@pred_trunc<mode>"
        (match_operand:VWEXTI 3 "register_operand"                 "  0,  0,  0,  0,   vr,   vr"))
      (match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand"     " vu,  0, vu,  0,   vu,    0")))]
   "TARGET_VECTOR"
-  "vncvt.x.x.w\t%0,%3%p1"
+  "%^vncvt.x.x.w\t%0,%3%p1"
   [(set_attr "type" "vnshift")
    (set_attr "mode" "<V_DOUBLE_TRUNC>")
    (set_attr "vl_op_idx" "4")
@@ -4028,14 +4051,14 @@ (define_insn "@pred_<optab><mode>"
      (match_operand:VI 2 "vector_merge_operand"     " vu,  0, vu,  0, vu,  0, vu,  0")))]
   "TARGET_VECTOR"
   "@
-   v<insn>.vv\t%0,%3,%4%p1
-   v<insn>.vv\t%0,%3,%4%p1
-   v<insn>.vv\t%0,%3,%4%p1
-   v<insn>.vv\t%0,%3,%4%p1
-   v<binop_vi_variant_insn>\t%0,<binop_vi_variant_op>%p1
-   v<binop_vi_variant_insn>\t%0,<binop_vi_variant_op>%p1
-   v<binop_vi_variant_insn>\t%0,<binop_vi_variant_op>%p1
-   v<binop_vi_variant_insn>\t%0,<binop_vi_variant_op>%p1"
+   %^v<insn>.vv\t%0,%3,%4%p1
+   %^v<insn>.vv\t%0,%3,%4%p1
+   %^v<insn>.vv\t%0,%3,%4%p1
+   %^v<insn>.vv\t%0,%3,%4%p1
+   %^v<binop_vi_variant_insn>\t%0,<binop_vi_variant_op>%p1
+   %^v<binop_vi_variant_insn>\t%0,<binop_vi_variant_op>%p1
+   %^v<binop_vi_variant_insn>\t%0,<binop_vi_variant_op>%p1
+   %^v<binop_vi_variant_insn>\t%0,<binop_vi_variant_op>%p1"
   [(set_attr "type" "<int_binop_insn_type>")
    (set_attr "mode" "<MODE>")])

@@ -4057,7 +4080,7 @@ (define_insn "@pred_<optab><mode>_scalar"
        (match_operand:VI_QHS 3 "register_operand"   " vr, vr, vr, vr"))
      (match_operand:VI_QHS 2 "vector_merge_operand" " vu,  0, vu,  0")))]
   "TARGET_VECTOR"
-  "v<insn>.vx\t%0,%3,%4%p1"
+  "%^v<insn>.vx\t%0,%3,%4%p1"
   [(set_attr "type" "<int_binop_insn_type>")
    (set_attr "mode" "<MODE>")])

@@ -4078,7 +4101,7 @@ (define_insn "@pred_<optab><mode>_scalar"
          (match_operand:<VEL> 4 "register_operand"  "  r,  r,  r,  r")))
      (match_operand:VI_QHS 2 "vector_merge_operand" " vu,  0, vu,  0")))]
   "TARGET_VECTOR"
-  "v<insn>.vx\t%0,%3,%4%p1"
+  "%^v<insn>.vx\t%0,%3,%4%p1"
   [(set_attr "type" "<int_binop_insn_type>")
    (set_attr "mode" "<MODE>")])

@@ -4132,7 +4155,7 @@ (define_insn "*pred_<optab><mode>_scalar"
        (match_operand:VI_D 3 "register_operand"     " vr, vr, vr, vr"))
      (match_operand:VI_D 2 "vector_merge_operand"   " vu,  0, vu,  0")))]
   "TARGET_VECTOR"
-  "v<insn>.vx\t%0,%3,%4%p1"
+  "%^v<insn>.vx\t%0,%3,%4%p1"
   [(set_attr "type" "<int_binop_insn_type>")
    (set_attr "mode" "<MODE>")])

@@ -4154,7 +4177,7 @@ (define_insn "*pred_<optab><mode>_extended_scalar"
        (match_operand:VI_D 3 "register_operand"         " vr, vr, vr, vr"))
      (match_operand:VI_D 2 "vector_merge_operand"       " vu,  0, vu,  0")))]
   "TARGET_VECTOR"
-  "v<insn>.vx\t%0,%3,%4%p1"
+  "%^v<insn>.vx\t%0,%3,%4%p1"
   [(set_attr "type" "<int_binop_insn_type>")
    (set_attr "mode" "<MODE>")])

@@ -4208,7 +4231,7 @@ (define_insn "*pred_<optab><mode>_scalar"
          (match_operand:<VEL> 4 "register_operand"  "  r,  r,  r,  r")))
      (match_operand:VI_D 2 "vector_merge_operand"   " vu,  0, vu,  0")))]
   "TARGET_VECTOR"
-  "v<insn>.vx\t%0,%3,%4%p1"
+  "%^v<insn>.vx\t%0,%3,%4%p1"
   [(set_attr "type" "<int_binop_insn_type>")
    (set_attr "mode" "<MODE>")])

@@ -4230,7 +4253,7 @@ (define_insn "*pred_<optab><mode>_extended_scalar"
            (match_operand:<VSUBEL> 4 "register_operand" "  r,  r,  r,  r"))))
      (match_operand:VI_D 2 "vector_merge_operand"       " vu,  0, vu,  0")))]
   "TARGET_VECTOR"
-  "v<insn>.vx\t%0,%3,%4%p1"
+  "%^v<insn>.vx\t%0,%3,%4%p1"
   [(set_attr "type" "<int_binop_insn_type>")
    (set_attr "mode" "<MODE>")])

@@ -4252,7 +4275,7 @@ (define_insn "@pred_<sat_op><mode>"
         (match_operand:VI 4 "register_operand"      " vr, vr, vr, vr")] VSAT_OP)
      (match_operand:VI 2 "vector_merge_operand"     " vu,  0, vu,  0")))]
   "TARGET_VECTOR"
-  "v<sat_op>.vv\t%0,%3,%4%p1"
+  "%^v<sat_op>.vv\t%0,%3,%4%p1"
   [(set_attr "type" "<sat_insn_type>")
    (set_attr "mode" "<MODE>")])

@@ -4275,7 +4298,7 @@ (define_insn "@pred_<sat_op><mode>_scalar"
         (match_operand:<VEL> 4 "reg_or_0_operand"   " rJ, rJ, rJ, rJ")] VSAT_ARITH_OP)
      (match_operand:VI_QHS 2 "vector_merge_operand" " vu,  0, vu,  0")))]
   "TARGET_VECTOR"
-  "v<sat_op>.vx\t%0,%3,%z4%p1"
+  "%^v<sat_op>.vx\t%0,%3,%z4%p1"
   [(set_attr "type" "<sat_insn_type>")
    (set_attr "mode" "<MODE>")])

@@ -4297,7 +4320,7 @@ (define_insn "@pred_<sat_op><mode>_scalar"
         (match_operand 4 "pmode_reg_or_uimm5_operand" " rK, rK, rK, rK")] VSAT_SHIFT_OP)
      (match_operand:VI 2 "vector_merge_operand"       " vu,  0, vu,  0")))]
   "TARGET_VECTOR"
-  "v<sat_op>.v%o4\t%0,%3,%4%p1"
+  "%^v<sat_op>.v%o4\t%0,%3,%4%p1"
   [(set_attr "type" "<sat_insn_type>")
    (set_attr "mode" "<MODE>")])

@@ -4355,7 +4378,7 @@ (define_insn "*pred_<sat_op><mode>_scalar"
         (match_operand:<VEL> 4 "reg_or_0_operand"   " rJ, rJ, rJ, rJ")] VSAT_ARITH_OP)
      (match_operand:VI_D 2 "vector_merge_operand"   " vu,  0, vu,  0")))]
   "TARGET_VECTOR"
-  "v<sat_op>.vx\t%0,%3,%z4%p1"
+  "%^v<sat_op>.vx\t%0,%3,%z4%p1"
   [(set_attr "type" "<sat_insn_type>")
    (set_attr "mode" "<MODE>")])

@@ -4378,7 +4401,7 @@ (define_insn "*pred_<sat_op><mode>_extended_scalar"
           (match_operand:<VSUBEL> 4 "reg_or_0_operand" " rJ, rJ, rJ, rJ"))] VSAT_ARITH_OP)
      (match_operand:VI_D 2 "vector_merge_operand"      " vu,  0, vu,  0")))]
   "TARGET_VECTOR"
-  "v<sat_op>.vx\t%0,%3,%z4%p1"
+  "%^v<sat_op>.vx\t%0,%3,%z4%p1"
   [(set_attr "type" "<sat_insn_type>")
    (set_attr "mode" "<MODE>")])

@@ -4401,7 +4424,7 @@ (define_insn "@pred_narrow_clip<v_su><mode>"
         (match_operand:<V_DOUBLE_TRUNC> 4 "vector_shift_operand"  "  0, 0,  0,  0,vr, vr,   vr,   vr, vk, vk,   vk,   vk")] VNCLIP)
      (match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand"     "  0,vu,  0, vu,vu, vu,   vu,    0, vu, vu,   vu,    0")))]
   "TARGET_VECTOR"
-  "vnclip<v_su>.w%o4\t%0,%3,%v4%p1"
+  "%^vnclip<v_su>.w%o4\t%0,%3,%v4%p1"
   [(set_attr "type" "vnclip")
    (set_attr "mode" "<V_DOUBLE_TRUNC>")])

@@ -4423,7 +4446,7 @@ (define_insn "@pred_narrow_clip<v_su><mode>_scalar"
         (match_operand 4 "pmode_reg_or_uimm5_operand"             " rK, rK, rK, rK,   rK,   rK")] VNCLIP)
      (match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand"     " vu,  0, vu,  0,   vu,    0")))]
   "TARGET_VECTOR"
-  "vnclip<v_su>.w%o4\t%0,%3,%4%p1"
+  "%^vnclip<v_su>.w%o4\t%0,%3,%4%p1"
   [(set_attr "type" "vnclip")
    (set_attr "mode" "<V_DOUBLE_TRUNC>")])

@@ -4466,7 +4489,7 @@ (define_insn "*pred_cmp<mode>_merge_tie_mask"
          (match_operand:V_VLSI 4 "vector_arith_operand"     "vrvi")])
      (match_dup 1)))]
   "TARGET_VECTOR"
-  "vms%B2.v%o4\t%0,%3,%v4,v0.t"
+  "%^vms%B2.v%o4\t%0,%3,%v4,v0.t"
   [(set_attr "type" "vicmp")
    (set_attr "mode" "<MODE>")
    (set_attr "merge_op_idx" "1")
@@ -4490,7 +4513,7 @@ (define_insn "*pred_cmp<mode>"
          (match_operand:V_VLSI 5 "vector_arith_operand"      "   vr,   vr,   vi,   vi")])
      (match_operand:<VM> 2 "vector_merge_operand"        "   vu,    0,   vu,    0")))]
   "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
-  "vms%B3.v%o5\t%0,%4,%v5%p1"
+  "%^vms%B3.v%o5\t%0,%4,%v5%p1"
   [(set_attr "type" "vicmp")
    (set_attr "mode" "<MODE>")])

@@ -4510,7 +4533,7 @@ (define_insn "*pred_cmp<mode>_narrow"
          (match_operand:V_VLSI 5 "vector_arith_operand"      " vrvi, vrvi,    0,    0, vrvi,    0,    0, vrvi, vrvi")])
      (match_operand:<VM> 2 "vector_merge_operand"        "   vu,   vu,   vu,   vu,    0,    0,    0,   vu,    0")))]
   "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
-  "vms%B3.v%o5\t%0,%4,%v5%p1"
+  "%^vms%B3.v%o5\t%0,%4,%v5%p1"
   [(set_attr "type" "vicmp")
    (set_attr "mode" "<MODE>")])

@@ -4546,7 +4569,7 @@ (define_insn "*pred_ltge<mode>_merge_tie_mask"
          (match_operand:V_VLSI 4 "vector_neg_arith_operand" "vrvj")])
      (match_dup 1)))]
   "TARGET_VECTOR"
-  "vms%B2.v%o4\t%0,%3,%v4,v0.t"
+  "%^vms%B2.v%o4\t%0,%3,%v4,v0.t"
   [(set_attr "type" "vicmp")
    (set_attr "mode" "<MODE>")
    (set_attr "merge_op_idx" "1")
@@ -4570,7 +4593,7 @@ (define_insn "*pred_ltge<mode>"
          (match_operand:V_VLSI 5 "vector_neg_arith_operand"  "   vr,   vr,   vj,   vj")])
      (match_operand:<VM> 2 "vector_merge_operand"        "   vu,    0,   vu,    0")))]
   "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
-  "vms%B3.v%o5\t%0,%4,%v5%p1"
+  "%^vms%B3.v%o5\t%0,%4,%v5%p1"
   [(set_attr "type" "vicmp")
    (set_attr "mode" "<MODE>")])

@@ -4590,7 +4613,7 @@ (define_insn "*pred_ltge<mode>_narrow"
          (match_operand:V_VLSI 5 "vector_neg_arith_operand"  " vrvj, vrvj,    0,    0, vrvj,    0,    0, vrvj, vrvj")])
      (match_operand:<VM> 2 "vector_merge_operand"        "   vu,   vu,   vu,   vu,    0,    0,    0,   vu,    0")))]
   "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
-  "vms%B3.v%o5\t%0,%4,%v5%p1"
+  "%^vms%B3.v%o5\t%0,%4,%v5%p1"
   [(set_attr "type" "vicmp")
    (set_attr "mode" "<MODE>")])

@@ -4628,7 +4651,7 @@ (define_insn "*pred_cmp<mode>_scalar_merge_tie_mask"
            (match_operand:<VEL> 4 "register_operand"      "  r"))])
      (match_dup 1)))]
   "TARGET_VECTOR"
-  "vms%B2.vx\t%0,%3,%4,v0.t"
+  "%^vms%B2.vx\t%0,%3,%4,v0.t"
   [(set_attr "type" "vicmp")
    (set_attr "mode" "<MODE>")
    (set_attr "merge_op_idx" "1")
@@ -4653,7 +4676,7 @@ (define_insn "*pred_cmp<mode>_scalar"
            (match_operand:<VEL> 5 "register_operand"     "    r,    r"))])
      (match_operand:<VM> 2 "vector_merge_operand"        "   vu,    0")))]
   "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
-  "vms%B3.vx\t%0,%4,%5%p1"
+  "%^vms%B3.vx\t%0,%4,%5%p1"
   [(set_attr "type" "vicmp")
    (set_attr "mode" "<MODE>")])

@@ -4674,7 +4697,7 @@ (define_insn "*pred_cmp<mode>_scalar_narrow"
            (match_operand:<VEL> 5 "register_operand"  "    r,    r,    r,    r,    r"))])
      (match_operand:<VM> 2 "vector_merge_operand"     "   vu,   vu,    0,   vu,    0")))]
   "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
-  "vms%B3.vx\t%0,%4,%5%p1"
+  "%^vms%B3.vx\t%0,%4,%5%p1"
   [(set_attr "type" "vicmp")
    (set_attr "mode" "<MODE>")])

@@ -4712,7 +4735,7 @@ (define_insn "*pred_eqne<mode>_scalar_merge_tie_mask"
          (match_operand:V_VLSI_QHS 3 "register_operand"        " vr")])
      (match_dup 1)))]
   "TARGET_VECTOR"
-  "vms%B2.vx\t%0,%3,%4,v0.t"
+  "%^vms%B2.vx\t%0,%3,%4,v0.t"
   [(set_attr "type" "vicmp")
    (set_attr "mode" "<MODE>")
    (set_attr "merge_op_idx" "1")
@@ -4737,7 +4760,7 @@ (define_insn "*pred_eqne<mode>_scalar"
          (match_operand:V_VLSI_QHS 4 "register_operand"      "   vr,   vr")])
      (match_operand:<VM> 2 "vector_merge_operand"        "   vu,    0")))]
   "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
-  "vms%B3.vx\t%0,%4,%5%p1"
+  "%^vms%B3.vx\t%0,%4,%5%p1"
   [(set_attr "type" "vicmp")
    (set_attr "mode" "<MODE>")])

@@ -4758,7 +4781,7 @@ (define_insn "*pred_eqne<mode>_scalar_narrow"
          (match_operand:V_VLSI_QHS 4 "register_operand"      "   vr,    0,    0,   vr,   vr")])
      (match_operand:<VM> 2 "vector_merge_operand"        "   vu,   vu,    0,   vu,    0")))]
   "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
-  "vms%B3.vx\t%0,%4,%5%p1"
+  "%^vms%B3.vx\t%0,%4,%5%p1"
   [(set_attr "type" "vicmp")
    (set_attr "mode" "<MODE>")])

@@ -4853,7 +4876,7 @@ (define_insn "*pred_cmp<mode>_scalar_merge_tie_mask"
            (match_operand:<VEL> 4 "register_operand"       "  r"))])
      (match_dup 1)))]
   "TARGET_VECTOR"
-  "vms%B2.vx\t%0,%3,%4,v0.t"
+  "%^vms%B2.vx\t%0,%3,%4,v0.t"
   [(set_attr "type" "vicmp")
    (set_attr "mode" "<MODE>")
    (set_attr "merge_op_idx" "1")
@@ -4877,7 +4900,7 @@ (define_insn "*pred_eqne<mode>_scalar_merge_tie_mask"
          (match_operand:V_VLSI_D 3 "register_operand"          " vr")])
      (match_dup 1)))]
   "TARGET_VECTOR"
-  "vms%B2.vx\t%0,%3,%4,v0.t"
+  "%^vms%B2.vx\t%0,%3,%4,v0.t"
   [(set_attr "type" "vicmp")
    (set_attr "mode" "<MODE>")
    (set_attr "merge_op_idx" "1")
@@ -4902,7 +4925,7 @@ (define_insn "*pred_cmp<mode>_scalar"
            (match_operand:<VEL> 5 "register_operand"     "    r,    r"))])
      (match_operand:<VM> 2 "vector_merge_operand"        "   vu,    0")))]
   "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
-  "vms%B3.vx\t%0,%4,%5%p1"
+  "%^vms%B3.vx\t%0,%4,%5%p1"
   [(set_attr "type" "vicmp")
    (set_attr "mode" "<MODE>")])

@@ -4923,7 +4946,7 @@ (define_insn "*pred_cmp<mode>_scalar_narrow"
            (match_operand:<VEL> 5 "register_operand"  "    r,    r,    r,    r,    r"))])
      (match_operand:<VM> 2 "vector_merge_operand"     "   vu,   vu,    0,   vu,    0")))]
   "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
-  "vms%B3.vx\t%0,%4,%5%p1"
+  "%^vms%B3.vx\t%0,%4,%5%p1"
   [(set_attr "type" "vicmp")
    (set_attr "mode" "<MODE>")])

@@ -4944,7 +4967,7 @@ (define_insn "*pred_eqne<mode>_scalar"
          (match_operand:V_VLSI_D 4 "register_operand"        "   vr,   vr")])
      (match_operand:<VM> 2 "vector_merge_operand"        "   vu,    0")))]
   "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
-  "vms%B3.vx\t%0,%4,%5%p1"
+  "%^vms%B3.vx\t%0,%4,%5%p1"
   [(set_attr "type" "vicmp")
    (set_attr "mode" "<MODE>")])

@@ -4965,7 +4988,7 @@ (define_insn "*pred_eqne<mode>_scalar_narrow"
          (match_operand:V_VLSI_D 4 "register_operand"        "   vr,    0,    0,   vr,   vr")])
      (match_operand:<VM> 2 "vector_merge_operand"        "   vu,   vu,    0,   vu,    0")))]
   "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
-  "vms%B3.vx\t%0,%4,%5%p1"
+  "%^vms%B3.vx\t%0,%4,%5%p1"
   [(set_attr "type" "vicmp")
    (set_attr "mode" "<MODE>")])

@@ -4986,7 +5009,7 @@ (define_insn "*pred_cmp<mode>_extended_scalar_merge_tie_mask"
              (match_operand:<VSUBEL> 4 "register_operand" "  r")))])
      (match_dup 1)))]
   "TARGET_VECTOR"
-  "vms%B2.vx\t%0,%3,%4,v0.t"
+  "%^vms%B2.vx\t%0,%3,%4,v0.t"
   [(set_attr "type" "vicmp")
    (set_attr "mode" "<MODE>")
    (set_attr "merge_op_idx" "1")
@@ -5012,7 +5035,7 @@ (define_insn "*pred_cmp<mode>_extended_scalar"
              (match_operand:<VSUBEL> 5 "register_operand" "    r,    r")))])
      (match_operand:<VM> 2 "vector_merge_operand"         "   vu,    0")))]
   "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
-  "vms%B3.vx\t%0,%4,%5%p1"
+  "%^vms%B3.vx\t%0,%4,%5%p1"
   [(set_attr "type" "vicmp")
    (set_attr "mode" "<MODE>")])

@@ -5033,7 +5056,7 @@ (define_insn "*pred_cmp<mode>_extended_scalar_narrow"
              (match_operand:<VSUBEL> 5 "register_operand" "    r,    r,    r,    r,    r")))])
      (match_operand:<VM> 2 "vector_merge_operand"         "   vu,   vu,    0,   vu,    0")))]
   "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
-  "vms%B3.vx\t%0,%4,%5%p1"
+  "%^vms%B3.vx\t%0,%4,%5%p1"
   [(set_attr "type" "vicmp")
    (set_attr "mode" "<MODE>")])

@@ -5054,7 +5077,7 @@ (define_insn "*pred_eqne<mode>_extended_scalar_merge_tie_mask"
          (match_operand:V_VLSI_D 3 "register_operand"           " vr")])
      (match_dup 1)))]
   "TARGET_VECTOR"
-  "vms%B2.vx\t%0,%3,%4,v0.t"
+  "%^vms%B2.vx\t%0,%3,%4,v0.t"
   [(set_attr "type" "vicmp")
    (set_attr "mode" "<MODE>")
    (set_attr "merge_op_idx" "1")
@@ -5080,7 +5103,7 @@ (define_insn "*pred_eqne<mode>_extended_scalar"
          (match_operand:V_VLSI_D 4 "register_operand"         "   vr,   vr")])
      (match_operand:<VM> 2 "vector_merge_operand"         "   vu,    0")))]
   "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
-  "vms%B3.vx\t%0,%4,%5%p1"
+  "%^vms%B3.vx\t%0,%4,%5%p1"
   [(set_attr "type" "vicmp")
    (set_attr "mode" "<MODE>")])

@@ -5101,7 +5124,7 @@ (define_insn "*pred_eqne<mode>_extended_scalar_narrow"
          (match_operand:V_VLSI_D 4 "register_operand"         "   vr,    0,    0,   vr,   vr")])
      (match_operand:<VM> 2 "vector_merge_operand"         "   vu,   vu,    0,   vu,    0")))]
   "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
-  "vms%B3.vx\t%0,%4,%5%p1"
+  "%^vms%B3.vx\t%0,%4,%5%p1"
   [(set_attr "type" "vicmp")
    (set_attr "mode" "<MODE>")])

@@ -5270,12 +5293,12 @@ (define_insn "*pred_mul_plus<mode>_undef"
      (match_operand:V_VLSI 2 "vector_undef_operand")))]
   "TARGET_VECTOR"
   "@
-   vmadd.vv\t%0,%4,%5%p1
-   vmacc.vv\t%0,%3,%4%p1
-   vmv.v.v\t%0,%4\;vmacc.vv\t%0,%3,%4%p1
-   vmadd.vv\t%0,%4,%5%p1
-   vmacc.vv\t%0,%3,%4%p1
-   vmv.v.v\t%0,%5\;vmacc.vv\t%0,%3,%4%p1"
+   %^vmadd.vv\t%0,%4,%5%p1
+   %^vmacc.vv\t%0,%3,%4%p1
+   %^vmv.v.v\t%0,%4\;%^vmacc.vv\t%0,%3,%4%p1
+   %^vmadd.vv\t%0,%4,%5%p1
+   %^vmacc.vv\t%0,%3,%4%p1
+   %^vmv.v.v\t%0,%5\;%^vmacc.vv\t%0,%3,%4%p1"
   [(set_attr "type" "vimuladd")
    (set_attr "mode" "<MODE>")])

@@ -5298,10 +5321,10 @@ (define_insn "*pred_madd<mode>"
      (match_dup 2)))]
   "TARGET_VECTOR"
   "@
-   vmadd.vv\t%0,%3,%4%p1
-   vmv.v.v\t%0,%2\;vmadd.vv\t%0,%3,%4%p1
-   vmadd.vv\t%0,%3,%4%p1
-   vmv.v.v\t%0,%2\;vmadd.vv\t%0,%3,%4%p1"
+   %^vmadd.vv\t%0,%3,%4%p1
+   %^vmv.v.v\t%0,%2\;%^vmadd.vv\t%0,%3,%4%p1
+   %^vmadd.vv\t%0,%3,%4%p1
+   %^vmv.v.v\t%0,%2\;%^vmadd.vv\t%0,%3,%4%p1"
   [(set_attr "type" "vimuladd")
    (set_attr "mode" "<MODE>")
    (set_attr "merge_op_idx" "4")
@@ -5329,10 +5352,10 @@ (define_insn "*pred_macc<mode>"
      (match_dup 4)))]
   "TARGET_VECTOR"
   "@
-   vmacc.vv\t%0,%2,%3%p1
-   vmv.v.v\t%0,%4\;vmacc.vv\t%0,%2,%3%p1
-   vmacc.vv\t%0,%2,%3%p1
-   vmv.v.v\t%0,%4\;vmacc.vv\t%0,%2,%3%p1"
+   %^vmacc.vv\t%0,%2,%3%p1
+   %^vmv.v.v\t%0,%4\;%^vmacc.vv\t%0,%2,%3%p1
+   %^vmacc.vv\t%0,%2,%3%p1
+   %^vmv.v.v\t%0,%4\;%^vmacc.vv\t%0,%2,%3%p1"
   [(set_attr "type" "vimuladd")
    (set_attr "mode" "<MODE>")
    (set_attr "merge_op_idx" "2")
@@ -5382,10 +5405,10 @@ (define_insn "*pred_madd<mode>_scalar"
      (match_dup 3)))]
   "TARGET_VECTOR"
   "@
-   vmadd.vx\t%0,%2,%4%p1
-   vmv.v.v\t%0,%3\;vmadd.vx\t%0,%2,%4%p1
-   vmadd.vx\t%0,%2,%4%p1
-   vmv.v.v\t%0,%3\;vmadd.vx\t%0,%2,%4%p1"
+   %^vmadd.vx\t%0,%2,%4%p1
+   %^vmv.v.v\t%0,%3\;%^vmadd.vx\t%0,%2,%4%p1
+   %^vmadd.vx\t%0,%2,%4%p1
+   %^vmv.v.v\t%0,%3\;%^vmadd.vx\t%0,%2,%4%p1"
   [(set_attr "type" "vimuladd")
    (set_attr "mode" "<MODE>")
    (set_attr "merge_op_idx" "4")
@@ -5414,10 +5437,10 @@ (define_insn "*pred_macc<mode>_scalar"
      (match_dup 4)))]
   "TARGET_VECTOR"
   "@
-   vmacc.vx\t%0,%2,%3%p1
-   vmv.v.v\t%0,%4\;vmacc.vx\t%0,%2,%3%p1
-   vmacc.vx\t%0,%2,%3%p1
-   vmv.v.v\t%0,%4\;vmacc.vx\t%0,%2,%3%p1"
+   %^vmacc.vx\t%0,%2,%3%p1
+   %^vmv.v.v\t%0,%4\;%^vmacc.vx\t%0,%2,%3%p1
+   %^vmacc.vx\t%0,%2,%3%p1
+   %^vmv.v.v\t%0,%4\;%^vmacc.vx\t%0,%2,%3%p1"
   [(set_attr "type" "vimuladd")
    (set_attr "mode" "<MODE>")
    (set_attr "merge_op_idx" "2")
@@ -5482,10 +5505,10 @@ (define_insn "*pred_madd<mode>_extended_scalar"
      (match_dup 3)))]
   "TARGET_VECTOR"
   "@
-   vmadd.vx\t%0,%2,%4%p1
-   vmv.v.v\t%0,%2\;vmadd.vx\t%0,%2,%4%p1
-   vmadd.vx\t%0,%2,%4%p1
-   vmv.v.v\t%0,%2\;vmadd.vx\t%0,%2,%4%p1"
+   %^vmadd.vx\t%0,%2,%4%p1
+   %^vmv.v.v\t%0,%2\;%^vmadd.vx\t%0,%2,%4%p1
+   %^vmadd.vx\t%0,%2,%4%p1
+   %^vmv.v.v\t%0,%2\;%^vmadd.vx\t%0,%2,%4%p1"
   [(set_attr "type" "vimuladd")
    (set_attr "mode" "<MODE>")
    (set_attr "merge_op_idx" "4")
@@ -5515,10 +5538,10 @@ (define_insn "*pred_macc<mode>_extended_scalar"
      (match_dup 4)))]
   "TARGET_VECTOR"
   "@
-   vmacc.vx\t%0,%2,%3%p1
-   vmv.v.v\t%0,%4\;vmacc.vx\t%0,%2,%3%p1
-   vmacc.vx\t%0,%2,%3%p1
-   vmv.v.v\t%0,%4\;vmacc.vx\t%0,%2,%3%p1"
+   %^vmacc.vx\t%0,%2,%3%p1
+   %^vmv.v.v\t%0,%4\;%^vmacc.vx\t%0,%2,%3%p1
+   %^vmacc.vx\t%0,%2,%3%p1
+   %^vmv.v.v\t%0,%4\;%^vmacc.vx\t%0,%2,%3%p1"
   [(set_attr "type" "vimuladd")
    (set_attr "mode" "<MODE>")
    (set_attr "merge_op_idx" "2")
@@ -5568,12 +5591,12 @@ (define_insn "*pred_minus_mul<mode>_undef"
      (match_operand:V_VLSI 2 "vector_undef_operand")))]
   "TARGET_VECTOR"
   "@
-   vnmsub.vv\t%0,%4,%5%p1
-   vnmsac.vv\t%0,%3,%4%p1
-   vmv.v.v\t%0,%3\;vnmsub.vv\t%0,%4,%5%p1
-   vnmsub.vv\t%0,%4,%5%p1
-   vnmsac.vv\t%0,%3,%4%p1
-   vmv.v.v\t%0,%3\;vnmsub.vv\t%0,%4,%5%p1"
+   %^vnmsub.vv\t%0,%4,%5%p1
+   %^vnmsac.vv\t%0,%3,%4%p1
+   %^vmv.v.v\t%0,%3\;%^vnmsub.vv\t%0,%4,%5%p1
+   %^vnmsub.vv\t%0,%4,%5%p1
+   %^vnmsac.vv\t%0,%3,%4%p1
+   %^vmv.v.v\t%0,%3\;%^vnmsub.vv\t%0,%4,%5%p1"
   [(set_attr "type" "vimuladd")
    (set_attr "mode" "<MODE>")])

@@ -5596,10 +5619,10 @@ (define_insn "*pred_nmsub<mode>"
      (match_dup 2)))]
   "TARGET_VECTOR"
   "@
-   vnmsub.vv\t%0,%3,%4%p1
-   vmv.v.v\t%0,%2\;vnmsub.vv\t%0,%3,%4%p1
-   vnmsub.vv\t%0,%3,%4%p1
-   vmv.v.v\t%0,%2\;vnmsub.vv\t%0,%3,%4%p1"
+   %^vnmsub.vv\t%0,%3,%4%p1
+   %^vmv.v.v\t%0,%2\;%^vnmsub.vv\t%0,%3,%4%p1
+   %^vnmsub.vv\t%0,%3,%4%p1
+   %^vmv.v.v\t%0,%2\;%^vnmsub.vv\t%0,%3,%4%p1"
   [(set_attr "type" "vimuladd")
    (set_attr "mode" "<MODE>")
    (set_attr "merge_op_idx" "4")
@@ -5627,10 +5650,10 @@ (define_insn "*pred_nmsac<mode>"
      (match_dup 4)))]
   "TARGET_VECTOR"
   "@
-   vnmsac.vv\t%0,%2,%3%p1
-   vmv.v.v\t%0,%4\;vnmsac.vv\t%0,%2,%3%p1
-   vnmsac.vv\t%0,%2,%3%p1
-   vmv.v.v\t%0,%4\;vnmsac.vv\t%0,%2,%3%p1"
+   %^vnmsac.vv\t%0,%2,%3%p1
+   %^vmv.v.v\t%0,%4\;%^vnmsac.vv\t%0,%2,%3%p1
+   %^vnmsac.vv\t%0,%2,%3%p1
+   %^vmv.v.v\t%0,%4\;%^vnmsac.vv\t%0,%2,%3%p1"
   [(set_attr "type" "vimuladd")
    (set_attr "mode" "<MODE>")
    (set_attr "merge_op_idx" "2")
@@ -5680,10 +5703,10 @@ (define_insn "*pred_nmsub<mode>_scalar"
      (match_dup 3)))]
   "TARGET_VECTOR"
   "@
-   vnmsub.vx\t%0,%2,%4%p1
-   vmv.v.v\t%0,%3\;vnmsub.vx\t%0,%2,%4%p1
-   vnmsub.vx\t%0,%2,%4%p1
-   vmv.v.v\t%0,%3\;vnmsub.vx\t%0,%2,%4%p1"
+   %^vnmsub.vx\t%0,%2,%4%p1
+   %^vmv.v.v\t%0,%3\;%^vnmsub.vx\t%0,%2,%4%p1
+   %^vnmsub.vx\t%0,%2,%4%p1
+   %^vmv.v.v\t%0,%3\;%^vnmsub.vx\t%0,%2,%4%p1"
   [(set_attr "type" "vimuladd")
    (set_attr "mode" "<MODE>")
    (set_attr "merge_op_idx" "4")
@@ -5712,10 +5735,10 @@ (define_insn "*pred_nmsac<mode>_scalar"
      (match_dup 4)))]
   "TARGET_VECTOR"
   "@
-   vnms

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ewlu / gcc-precommit-ci