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Patch Status 27667-Committed_RISCV_Rename_vconstraint_into_groupoverlap-1 #799

Closed github-actions[bot] closed 10 months ago

github-actions[bot] commented 10 months ago

Precommit CI Run information

Logs can be found in the associated Github Actions run: https://github.com/ewlu/gcc-precommit-ci/actions/runs/7039722703

Patch information

Applied patches: 1 -> 1 Associated series: https://patchwork.sourceware.org/project/gcc/list/?series=27667 Last patch applied: https://patchwork.sourceware.org/project/gcc/patch/20231129231446.204221-1-juzhe.zhong@rivai.ai/ Patch id: 80993

Build Targets

Some targets are built as multilibs. If a build target ends with multilib, please refer to the table below to see all the targets within that multilib. Target name -march string
newlib-rv64gc-lp64d-multilib rv32gc-ilp32d, rv64gc-lp64d
newlib-rv64gcv-lp64d-multilib rv64gcv-lp64d
linux-rv64gcv-lp64d-multilib rv32gcv-ilp32d, rv64gcv-lp64d

Target Information

Target Shorthand -march string
Bitmanip gc_zba_zbb_zbc_zbs

Notes

Testsuite results use a more lenient allowlist to reduce error reporting with flakey tests. Please take a look at the current allowlist. Results come from a sum file comparator. Each patch is applied to a well known, non-broken baseline taken from our gcc postcommit framework (here) which runs the full gcc testsuite every 6 hours. If you have any questions or encounter any issues which may seem like false-positives, please contact us at patchworks-ci@rivosinc.com

github-actions[bot] commented 10 months ago

Lint Status

The following issues have been found with 27667-Committed_RISCV_Rename_vconstraint_into_groupoverlap-1 using gcc's ./contrib/check_GNU_style.py. Please use your best judgement when resolving these issues. These are only warnings and do not need to be resolved in order to merge your patch. If any of these warnings seem like false-positives that could be guarded against please contact me: patchworks-ci@rivosinc.com.

=== ERROR type #1: blocks of 8 spaces should be replaced with tabs (3 error(s)) ===
gcc/config/riscv/riscv.md:514:0:████████ (and (eq_attr "group_overlap" "W21")
gcc/config/riscv/riscv.md:518:0:████████ (and (eq_attr "group_overlap" "W42,W43")
gcc/config/riscv/riscv.md:522:0:████████ (and (eq_attr "group_overlap" "W84,W86,W87")

Additional information

github-actions[bot] commented 10 months ago

Apply Status

Target Status
Baseline hash: https://github.com/gcc-mirror/gcc/commit/b09b879e4e9cc24a5d2b0344c1930020c218a104 Failed
Tip of tree hash: https://github.com/gcc-mirror/gcc/commit/99d114c15523e0bfe7a89ef1947f82eb5ff0260b Failed

Command

> git am ../patches/*.patch --whitespace=fix -q --3way --empty=drop

Output

error: sha1 information is lacking or useless (gcc/config/riscv/vector.md).
error: could not build fake ancestor
hint: Use 'git am --show-current-patch=diff' to see the failed patch
Patch failed at 0001 RISC-V: Rename vconstraint into group_overlap
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
---
 gcc/config/riscv/constraints.md | 12 ++++++------
 gcc/config/riscv/riscv.md       | 21 ++++++++++++---------
 gcc/config/riscv/vector.md      |  4 ++--
 3 files changed, 20 insertions(+), 17 deletions(-)

diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index 19bb36616bf..9836fd34460 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -183,14 +183,14 @@
 (define_register_constraint "W84" "TARGET_VECTOR ? V_REGS : NO_REGS"
   "A vector register has register number % 8 == 4." "regno % 8 == 4")

-(define_register_constraint "W41" "TARGET_VECTOR ? V_REGS : NO_REGS"
-  "A vector register has register number % 4 == 1." "regno % 4 == 1")
+(define_register_constraint "W43" "TARGET_VECTOR ? V_REGS : NO_REGS"
+  "A vector register has register number % 4 == 3." "regno % 4 == 3")

-(define_register_constraint "W81" "TARGET_VECTOR ? V_REGS : NO_REGS"
-  "A vector register has register number % 8 == 1." "regno % 8 == 1")
+(define_register_constraint "W86" "TARGET_VECTOR ? V_REGS : NO_REGS"
+  "A vector register has register number % 8 == 6." "regno % 8 == 6")

-(define_register_constraint "W82" "TARGET_VECTOR ? V_REGS : NO_REGS"
-  "A vector register has register number % 8 == 2." "regno % 8 == 2")
+(define_register_constraint "W87" "TARGET_VECTOR ? V_REGS : NO_REGS"
+  "A vector register has register number % 8 == 7." "regno % 8 == 7")

 ;; This constraint is used to match instruction "csrr %0, vlenb" which is generated in "mov<mode>".
 ;; VLENB is a run-time constant which represent the vector register length in bytes.
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 6bf2dfdf9b4..4c6f63677df 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -501,22 +501,25 @@
   ]
   (const_string "no")))

-(define_attr "vconstraint" "no,W21,W42,W84,W41,W81,W82"
-  (const_string "no"))
-
-(define_attr "vconstraint_enabled" "no,yes"
-  (cond [(eq_attr "vconstraint" "no")
+;; Widening instructions have group-overlap constraints.  Those are only
+;; valid for certain register-group sizes.  This attribute marks the
+;; alternatives not matching the required register-group size as disabled.
+(define_attr "group_overlap" "none,W21,W42,W84,W43,W86,W87"
+  (const_string "none"))
+
+(define_attr "group_overlap_valid" "no,yes"
+  (cond [(eq_attr "group_overlap" "none")
          (const_string "yes")

-         (and (eq_attr "vconstraint" "W21")
+         (and (eq_attr "group_overlap" "W21")
          (match_test "riscv_get_v_regno_alignment (GET_MODE (operands[0])) != 2"))
     (const_string "no")

-         (and (eq_attr "vconstraint" "W42,W41")
+         (and (eq_attr "group_overlap" "W42,W43")
          (match_test "riscv_get_v_regno_alignment (GET_MODE (operands[0])) != 4"))
     (const_string "no")

-         (and (eq_attr "vconstraint" "W84,W81,W82")
+         (and (eq_attr "group_overlap" "W84,W86,W87")
          (match_test "riscv_get_v_regno_alignment (GET_MODE (operands[0])) != 8"))
     (const_string "no")
         ]
@@ -531,7 +534,7 @@
     (eq_attr "fp_vector_disabled" "yes")
     (const_string "no")

-    (eq_attr "vconstraint_enabled" "no")
+    (eq_attr "group_overlap_valid" "no")
     (const_string "no")
   ]
   (const_string "yes")))
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 5667f8bd2b6..74716c73e98 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -3700,7 +3700,7 @@
   "v<sz>ext.vf2\t%0,%3%p1"
   [(set_attr "type" "vext")
    (set_attr "mode" "<MODE>")
-   (set_attr "vconstraint" "W21,W21,W42,W42,W84,W84,no,no")])
+   (set_attr "group_overlap" "W21,W21,W42,W42,W84,W84,none,none")])

 ;; Vector Quad-Widening Sign-extend and Zero-extend.
 (define_insn "@pred_<optab><mode>_vf4"
@@ -3923,7 +3923,7 @@
    (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[5])"))
    (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
    (set (attr "avl_type_idx") (const_int 7))
-   (set_attr "vconstraint" "W21,W21,W42,W42,W84,W84,no,no")])
+   (set_attr "group_overlap" "W21,W21,W42,W42,W84,W84,none,none")])

 ;; -------------------------------------------------------------------------------
 ;; ---- Predicated integer Narrowing operations

Additional information