Language request for SystemVerilog

[Des333]

What programming language should we add? SystemVerilog (less preferably -- Verilog)

What is the official website for the language? There's no official website, but here are links to the standards:

• SystemVerilog (IEEE Standard 1800-2017) -- http://ecee.colorado.edu/~mathys/ecen2350/IntelSoftware/pdf/IEEE_Std1800-2017_8299595.pdf
• Verilog (IEEE 1364-2005) -- https://www.eg.bucknell.edu/~csci320/2016-fall/wp-content/uploads/2015/08/verilog-std-1364-2005.pdf

Is this a language that comes in many variants? If so, which variant should we support? In 2005 SystemVerilog was adopted as IEEE Standard 1800-2005. In 2009 the standard was merged with the base Verilog (IEEE 1364-2005) standard, creating IEEE Standard 1800-2009. The current version is IEEE standard 1800-2017.

SystemVerilog is a much more modern version of the language than Verilog. Fortunately the basic concepts and basic constructs are very similar (even closer as C and C++).

Does the language have an official logo? Yes.

• please include a link to an example: https://www.accellera.org/images/about/policies/logos/systemverilog-logo.png

• please list the attribution rights of that logo: https://www.accellera.org/about/policies-and-procedures/logo-use

  Accellera also has a number of secondary logos used for branding individual standards (SystemC, SystemVerilog, UPF, UVM, IP-XACT, VHDL). Permission for appropriate business use of these logos within the EDA industry for print and web applications is freely granted and encouraged. Inappropriate or abusive use of the secondary logos is prohibited.

Does the language have an unofficial logo? No

Is there a testing framework available for the language? For this language it is quite a difficult question. The Verilog and SystemVerilog languages ​​themselves were also created for writing testbenches and test frameworks (in addition to developing FPGA and ASIC firmwares). Therefore many features for testing are built into the language itself and also in standard methodologies (like OVM and UVM).

Also many features for testing are built into the simulators. There are many completely free and free for non-commercial use compilers and simulators:

• http://iverilog.icarus.com/home
• https://www.edaplayground.com
• http://fpgasoftware.intel.com/?edition=lite
• https://www.mentor.com/company/higher_ed/modelsim-student-edition

Open source testing frameworks also exist:

• https://github.com/VUnit/vunit
• https://github.com/tymonx/logic
• https://github.com/nosnhojn/svunit-code

Is this language listed as 'supported' by Prism.js? Yes, Verilog is supported by Prism.

• what is Prism's canonical spelling for the language -- verilog
• what file extensions should be highlighted -- .v and .sv

Who will be leading the effort to launch the track? Me (@Des333) and my colleague (@m1a1x1)

[kytrinyx]

Thanks so much @Des333. I will get this repository started for you in the next couple of days.

[kytrinyx]

Alrighty, this is now bootstrapped and ready for you: https://github.com/exercism/system-verilog/issues/1

Holler if you have questions!

[kytrinyx]

The work to launch this track was never completed, and there has been no activity on the track for a long time. We are therefore archiving the track repository.

If someone wants to actively build and launch this track, please open an issue in https://forum.exercism.org/c/exercism/building-exercism/125 to discuss it.