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system-verilog
Exercism exercises in SystemVerilog.
https://exercism.org/tracks/system-verilog
MIT License
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🤖 Add file patterns to config.json
#21
ErikSchierboom
closed
3 years ago
1
[v3] Update Markdown files to latest spec
#20
ErikSchierboom
closed
3 years ago
0
Launch Tracker 🔴
#19
ErikSchierboom
closed
1 year ago
0
Update status of Concept Exercises
#18
ErikSchierboom
closed
3 years ago
1
Update status of track
#17
ErikSchierboom
closed
1 year ago
0
Build Representer and Analyzer
#16
ErikSchierboom
closed
3 years ago
1
Build Test Runner
#15
ErikSchierboom
closed
1 year ago
0
Pass linting checks
#14
ErikSchierboom
closed
1 year ago
1
Add prerequisites to Practice Exercises
#13
ErikSchierboom
closed
1 year ago
1
Add tags
#12
ErikSchierboom
closed
1 year ago
0
Add key features
#11
ErikSchierboom
closed
1 year ago
0
Configure online editor
#10
ErikSchierboom
closed
1 year ago
1
[v3] Prepare for v3
#9
ErikSchierboom
closed
3 years ago
0
The master branch will be renamed to main
#8
ErikSchierboom
closed
3 years ago
1
[Important] The current website is about to enter maintenance mode to aid with v3 launch
#7
ErikSchierboom
closed
3 years ago
2
Replace Travis with GHA
#6
cmccandless
closed
3 years ago
0
Moving from Travis to GitHub Actions
#5
ErikSchierboom
closed
3 years ago
1
Add codeowner for maintainers.json file
#4
ErikSchierboom
closed
3 years ago
0
What was it like to learn SystemVerilog?
#3
ErikSchierboom
closed
3 years ago
1
Create stub files for all exercises
#2
kytrinyx
closed
1 year ago
0
Launch tracking
#1
kytrinyx
closed
1 year ago
2
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