sio break unreliably detected under slower f32c clock

[emard]

Valentin from FLEAsystems http://www.fleasystems.com/fleaFPGA.html succesfully ported f32c on his board with maximum stable core clock frequency of 55MHz and he's having issues with sio break detection timeouts.

this is how he fixed it in sio.vhd

Thanks to modifying the following line in sio.vhd, I am also now able to perform one-click upload from the Arduino IDE - very cool!! :-D constant C_break_detect_incr: integer := 1 + 33 / C_clk_freq; -- For 81.25MHz use: "1 + 50 / C_clk_freq;"

We should check timeouts in sio and ujprog and how they are calculated, to make them work more reliably on boundary cases

[emard]

I have improved sio.vhd math for precision timing of serial break detection which should be 200 ms real time, independent of cpu clock speed. I look forward for positive feedback from Valentin.

[emard]

Valentin reported improvement in being able to raise speed to 75 MHz but he had to raise serial break delay detection to 250 ms in sio.vhd

ujprog (windows) should be checked can it correctly handle when f32c resets mutiple times with mutiple prompts sent over serial line