Closed f4exb closed 4 years ago
On my side the 1 bit error tolerance on the NXDN sync pattern really improve the frame detection. Try it on your side if you want !
G4LX tolerate more errors on his MMDVM firmware (3 errors bits if I read correctly the code).
But as you said the FSW is really short in NXDN, so this improvement also introduce false positive frame detection, I tried to fix it with a good LICH detection but the only 1 parity bit is really short to check if the frame type is correct...
I think adding a frame storage buffer with a high level FSW bits counter/analyzer could reduce false positive detection, I'm studying this option on my side.
@LouisErigHerve Maybe you could help out on the other issue we are having ? Well i am not really having it I am just the guy witht he equipment to test but....https://github.com/f4exb/sdrangel/issues/574
Comparing at each new symbols the n previous symbols with each different sync sequence by looping each time on these previous symbols is not efficient. The DSDSymbol
class should accumulate the symbol differences against each sync sequence at each new symbol.
Implemented in v1.9.0
Down in this tweet here https://twitter.com/LouisErigHerve there is an interesting suggestion to tolerate some errors on the sync pattern in order to increase the probability to detect it mitigating false positives by not tolerating too many errors (just one for NXDN):
This deserves to be experimented at least and committed if it really improves things when conditions are not so good. It could even be extended to other modes. NXDN has the shortest sync sequence so if you introduce a 1 symbol tolerance on it and it works you can surely do the same for the others.
Edit: the tweet was just the initiator. The core of the improvement is actually here: https://github.com/LouisErigHerve/dsd/commit/b98276fddcaab0d2507a35a9d7ac77a6aa6a7d23