fasm2v failures - Githubissues

f4pga / f4pga-arch-defs

FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

https://f4pga.org

ISC License

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fasm2v failures #1018

Closed litghost closed 4 years ago

litghost commented 5 years ago

With https://github.com/verilog-to-routing/vtr-verilog-to-routing/pull/969, in theory fasm2v should have no differences with Vivado, except for bugs in either synth or fasm2v.

Targets that are passing:

[x] bram_test_18
[x] murax_basys
[x] dram_test_64x1d
[x] counter_basys3

Targets that failed during fasm2v:

[x] dram_test_32m

Targets that failed during Vivado:

[x] top_dram_n3
[x] dram_test_64m
[ ] srl32_doutmux_mc31
[ ] srl16_chain

Targets that have diffs:

[x] bram_test_36
[x] top_bram_n3
[x] picosoc_basys3
[x] srl16_doutmux_mc31

litghost commented 4 years ago

Vendor CI is currently green. Smaller issues exist to track re-enabling failing tests.