Open acomodi opened 4 years ago
FYI the tcl file generated for fasm2bels disable those loops: https://github.com/SymbiFlow/symbiflow-arch-defs/blob/master/xc7/utils/vivado_create_runme.py#L48
As for whether these loops are real, I believe they are not. In particular, fasm2bels shows higher LUT usage than a real design because of how it emits to verilog. I believe that the problem is that Vivado is not verifying if the LUT equations form a loop. If LUT A . O6 forms a loop with LUT B, but via an address line that doesn't affect O6, is that a Combinatorial loop?
GitHub
FOSS architecture definitions of FPGA hardware useful for doing PnR device generation. - SymbiFlow/symbiflow-arch-defs
Is this a case of a LUT6_2 where the O6 and O5 outputs are dependent only on a certain set of inputs? (IE can be thought of as two independent LUTs packed into the one primitive?)
On Fri, Jan 24, 2020, 3:43 PM litghost notifications@github.com wrote:
FYI the tcl file generated for fasm2bels disable those loops: https://github.com/SymbiFlow/symbiflow-arch-defs/blob/master/xc7/utils/vivado_create_runme.py#L48
As for whether these loops are real, I believe they are not. In particular, fasm2bels shows higher LUT usage than a real design because of how it emits to verilog. I believe that the problem is that Vivado is not verifying if the LUT equations form a loop. If LUT A . O6 forms a loop with LUT B, but via an address line that doesn't affect O6, is that a Combinatorial loop?
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Is this a case of a LUT6_2 where the O6 and O5 outputs are dependent only on a certain set of inputs? (IE can be thought of as two independent LUTs packed into the one primitive?)
That is my assumption.
When experimenting on the
antenna nets
generated with some designs for the artix50T, I encountered this issue after having rerouted the faulty antenna nets with Vivado (the design ismurax_basys_full
):I am unsure whether this is relative to the rerouting of the antenna nets with Vivado, or the issue is generated withing SymbiFlow.