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f4pga / f4pga-arch-defs

FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
https://f4pga.org
ISC License
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Get the carry chain on ice40 working #140

Open mithro opened 6 years ago

mithro commented 6 years ago

Probably dependent on https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/325

From http://www.clifford.at/icestorm/logic_tile.html

Input lutff_i/in_3 can be configured to be driven by the carry output of the previous logic cell, or by carry_in_mux in case of i=0.

The carry unit calculates lutff_i/cout = lutff_i/in_1 + lutff_i/in2 + lutff(i-1)/cout > 1. In case of i=0, carry_in_mux is used as third input. carry_in_mux can be configured to be constant 0, 1 or the lutff_7/cout signal from the logic tile below.

Find the description here -> https://github.com/SymbiFlow/symbiflow-arch-defs/tree/master/ice40/primitives/sb_carry

mithro commented 6 years ago

I'm working on this.