Create an ice40 test for the packing of different types of flip flops together

[mithro]

From http://www.clifford.at/icestorm/logic_tile.html

Clock, clock enable, and set/reset inputs are shared along the 8 logic cells. So is the bit that configures positive/negative edge for the flip flops. But the three configuration bits that specify if the flip flop should be used, if it is set or reset by the set/reset input, and if the set/reset is synchronous or asynchronous exist for each logic cell individually.

There also seem to be the following SB_FF models;

  <model name="SB_DFF">
  <model name="SB_DFFE">
  <model name="SB_DFFER">
  <model name="SB_DFFES">
  <model name="SB_DFFESR">
  <model name="SB_DFFESS">
  <model name="SB_DFFR">
  <model name="SB_DFFS">
  <model name="SB_DFFSR">
  <model name="SB_DFFSS">

This means you can only pack certain types of flip flops together into a tile. Need a test which explicitly looks for this.

[daveshah1]

As well as the primitives above there are also negative edge versions of each type.

[mithro]

There is one added here -> https://github.com/mithro/symbiflow-arch-defs/tree/4mcmaster/tests/ice40/ffpack

This needs https://github.com/verilog-to-routing/vtr-verilog-to-routing/pull/365 to be merged into VPR before it works.

GitHub

mithro/symbiflow-arch-defs

symbiflow-arch-defs - FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

[elms]

After some discussion, it seems like a good approach is to generate (with python) many possible strings of differing FF types and then use formal verification to compare the original to generated verilog from the asc file.

We think there are 20 types of FF

negclk	cen	SR	async	set_norest	type name	packs if the same
0	0	0	X	X	DFF	A
0	1	0	X	X	DFFE	B
0	0	1	0	0	DFFSR	C
0	0	1	0	1	DFFSS	C
0	0	1	1	0	DFFR	C
0	0	1	1	1	DFFS	C
0	1	1	0	1	DFFESS	D
0	1	1	0	0	DFFESR	D
0	1	1	1	0	DFFER	D
0	1	1	1	1	DFFES	D
1	0	0	X	X	DFFN	a
1	1	0	X	X	DFFNE	b
1	0	1	0	0	DFFNSR	c
1	0	1	0	1	DFFNSS	c
1	0	1	1	0	DFFNR	c
1	0	1	1	1	DFFNS	c
1	1	1	0	1	DFFNESS	d
1	1	1	0	0	DFFNESR	d
1	1	1	1	0	DFFNER	d
1	1	1	1	1	DFFNES	d