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f4pga / f4pga-arch-defs

FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
https://f4pga.org
ISC License
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Unknown HCLK_R bits #1529

Open rw1nkler opened 4 years ago

rw1nkler commented 4 years ago

After running BUFGMUX example on Nexys Video with limited grid I obtained the bitstream, which is not working correctly on the hardware. The diff_fasm step returns no differences between the FASMs generated by the vivado and symbiflow. In addition, a bitstream generated by the vivado in the diff_fasm step works correctly.

Here is the output of thebit2fasm.py script used on vivado diff_fasm bitstream:

{ unknown_bit = "00401b9a_43_4", unknown_segment = "0x00401b80", unknown_segbit = "26_1380" }
{ unknown_bit = "00401b9a_55_20", unknown_segment = "0x00401b80", unknown_segbit = "26_1780" }
{ unknown_bit = "00401b9a_98_14", unknown_segment = "0x00401b80", unknown_segbit = "26_3150" }

This leads to HCLK_R_X137Y130 in the xc7a200tffg1156-1 tilegrid.json. The features related to the HCLK_R are generated by the 058-pip-hclk fuzzer.

litghost commented 3 years ago

@rw1nkler Can you please create a PR that replicates this issue? Thanks.