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f4pga / f4pga-arch-defs

FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
https://f4pga.org
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Write a Python library for decoding Xilinx Series 7 wire names #181

Open mithro opened 6 years ago

mithro commented 6 years ago

The names of wires in the series-7 FPGA have meaning, for example SW4BEG0 might mean 'the beginning of a wire which runs south west 4 tiles'.

There is the start of some code here -> https://github.com/SymbiFlow/symbiflow-arch-defs/blob/474d3ed44647c1dc53eafddb16ba9eb0e025506a/artix7/utils/prjxray-routing-import.py#L308-L343

The Project X-Ray tileconn.json has a list of names we know.

But it would nice to have a proper library with tests and such.

mithro commented 5 years ago

@litghost Does this library exist somewhere?

litghost commented 5 years ago

We don't need it?

litghost commented 5 years ago

Also, in special cases, the interpretation is wrong. At the top and bottom of every INT tile are turn around blocks. I believe there are similiar constructs above large blocks, like PCI

mithro commented 5 years ago

I believe we do need this library as we want to be able to present to humans better names in the future.

BalasubramanyamEvani commented 5 years ago

Hi ! is this issue already assigned or still open to work on. I am new to the project and would like to contribute. Can anybody guide me through this ? Thank you.

mithro commented 5 years ago

@BalasubramanyamEvani This idea is still open to being done!

First step is to probably write up a short document which has a list of the wires from the FASM prjxray database and figure out what they mean in "human terms". Once that is done, it should be pretty easy to start writing some Python code to extract this information....

BalasubramanyamEvani commented 5 years ago

@mithro Ok got it ! I will start working upon it then. I will first go through the json file and find respective meanings of the wires, then work on the python script.

bangpradyumna commented 4 years ago

@mithro Is this issue still relevant and if yes, Can I please work on it ?

Thanks

mithro commented 4 years ago

Yes, this is still a relevant issue and anyone can work on it. (If you are thinking in terms of GSoC, it probably isn't big enough to be a GSoC project by itself.)