The auto-generated designs, such as litex, present some small variations in the memory initialization of the BRAMs. This causes a small perturbation in the initial conditions of a test, which lead to major changes in the output results.
This problem might not be only related to the BRAM initialization, but to any small changes that are applied to a specific design, but for the sake of this issue description, we will keep the small BRAM initialization changes as the triggering factor for this issue.
This issue covers the sensitivity of the synthesis step which produces two very different eblifs given a small change in the memory initialization values.
Packer
The perturbation in the nets ordering of the circuit might affect the way the packer acts. For instance, two different runs of the same test produced the following packing results:
Test 1:
Resource usage...
Netlist
1099 blocks of type: BLK-TL-SLICEL
Architecture
2150 blocks of type: BLK-TL-CLBLL_L
1200 blocks of type: BLK-TL-CLBLL_R
1800 blocks of type: BLK-TL-CLBLM_L
3000 blocks of type: BLK-TL-CLBLM_R
Test 2:
Resource usage...
Netlist
1114 blocks of type: BLK-TL-SLICEL
Architecture
2150 blocks of type: BLK-TL-CLBLL_L
1200 blocks of type: BLK-TL-CLBLL_R
1800 blocks of type: BLK-TL-CLBLM_L
3000 blocks of type: BLK-TL-CLBLM_R
The two Verilog descriptions of the design are identical, except for the memory initialization.
A possible solution to this behaviour is to make the packer algorithms more robust to changes in the ordering of the input circuit, making it less sensitive to changes in input conditions.
Placer
Initial placement is currently very sensitive to the seed. In fact, changing the seed can generate very different outcomes, in terms of CPD as well as router run-time.
This is proven by the following test, which, taken two initially equal packed netlists and two different SEEDs, the router behaviour drastically changed:
tcal-x
commented
2 years ago
This issue is to keep track of the issue reported here: https://github.com/SymbiFlow/symbiflow-arch-defs/issues/1776.
This issue has been split from https://github.com/SymbiFlow/symbiflow-arch-defs/issues/1788, as it tackles a different problem.
Problem statement
The auto-generated designs, such as litex, present some small variations in the memory initialization of the BRAMs. This causes a small perturbation in the initial conditions of a test, which lead to major changes in the output results.
This problem might not be only related to the BRAM initialization, but to any small changes that are applied to a specific design, but for the sake of this issue description, we will keep the small BRAM initialization changes as the triggering factor for this issue.
This issue covers the sensitivity of the synthesis step which produces two very different
eblifsgiven a small change in the memory initialization values.Packer
The perturbation in the nets ordering of the circuit might affect the way the packer acts. For instance, two different runs of the same test produced the following packing results:
Test 1:
Test 2:
The two Verilog descriptions of the design are identical, except for the memory initialization.
A possible solution to this behaviour is to make the packer algorithms more robust to changes in the ordering of the input circuit, making it less sensitive to changes in input conditions.
Placer
Initial placement is currently very sensitive to the seed. In fact, changing the seed can generate very different outcomes, in terms of CPD as well as router run-time.
This is proven by the following test, which, taken two initially equal packed netlists and two different SEEDs, the router behaviour drastically changed:
default seed:
custom seed (1000):
On a separate test, I have verified and confirmed that having exact same input conditions (seed, packed netlist, etc) produces the same outputs.
Steps to reproduce
arty_socdirectory.