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f4pga / f4pga-arch-defs

FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
https://f4pga.org
ISC License
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build(deps): bump third_party/pythondata-cpu-vexriscv from `a36d99e` to `1979a64` #3706

Closed dependabot[bot] closed 2 months ago

dependabot[bot] commented 2 months ago

Bumps third_party/pythondata-cpu-vexriscv from a36d99e to 1979a64.

Commits
  • 1979a64 sync verilog with previous commit
  • 8542a57 when --debug is used, a halted pin is added to VexRiscv for the user usages
  • 03d8c47 Merge pull request #20 from lschuermann/dev/pmp-plugin-switch
  • 1aead15 Update built Verilog targets
  • 63430af Add pmpAddressMatchingModes switch to select {PmpPlugin,PmpPluginNapot}
  • c36b1f3 Update VexRiscv to b6118e5cc2a3 of 2023-11-14, update sbt and SpinalHDL
  • See full diff in compare view


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