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f4pga / f4pga-arch-defs

FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
https://f4pga.org
ISC License
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build(deps): bump third_party/liteeth from `150710d` to `b573e12` #3876

Closed dependabot[bot] closed 2 weeks ago

dependabot[bot] commented 2 weeks ago

Bumps third_party/liteeth from 150710d to b573e12.

Commits
  • b573e12 phy/xgmii: Add Clk/Data Pads definition to avoid duplication in PHYs.
  • 78513c2 frontend/stream: Add 64-bit data_width support.
  • b1f916a frontend/etherbone: Add LiteEthLastHandler to LiteEthEtherbonePacketRX for 64...
  • 0b5389f mac: Move LiteEthMACLastBE module to common.py and rename to LiteEthLastHandler.
  • a2a862d liteeth_gen: Add XGMII PHY support (Transceiver still need to be integrated e...
  • 74bd085 Merge pull request #168 from trabucayre/efinix_rework_primitives
  • 9496fd2 phy/titaniumrgmii.py: uses ClockSignal for DDRInput/DDROutput/ClkOutput, adde...
  • 88387cb phy/trionrgmii.py: use ClockSignal for ClkOutput 'o', remove name parameter w...
  • 577a472 phy/trionrgmii.py: DDRInput/DDROutput switch clk to a ClockSignal
  • ea07f5c phy/titaniumrgmii,trionrgmii: fixed pll clkin name by appending a '0' to matc...
  • Additional commits viewable in compare view


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dependabot[bot] commented 2 weeks ago

Superseded by #3878.