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f4pga / f4pga-arch-defs

FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
https://f4pga.org
ISC License
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build(deps): bump third_party/litex from `95b310e` to `b2f63b3` #3891

Closed dependabot[bot] closed 1 week ago

dependabot[bot] commented 1 week ago

Bumps third_party/litex from 95b310e to b2f63b3.

Commits
  • b2f63b3 CHANGES.md: Update.
  • 427ec10 CONTRIBUTORS: Update.
  • 726d39f LICENSE: Bump year.
  • baff4c6 Merge pull request #2075 from trabucayre/efinix_clkinput_signal
  • 033ec13 Merge pull request #2076 from trabucayre/xc7s_jtag
  • 6e9dffd soc/core/hyperbus: Avoid combinatorial loop on write bursts (Reported when bu...
  • ad2c3fc soc/cores/cpu/vexiirscv: Add standard variant to allow compilation without sp...
  • f1e1f35 build/efinix/ifacewriter.py: allows the use of ClockSignal for IN_CLK_PIN (gpio)
  • aca959b build/efinix/common.py: ClkInput: added ClockSignal support
  • e072156 build/xilinx/platform.py: added xc7s to the list of device supporting jtag ac...
  • Additional commits viewable in compare view


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dependabot[bot] commented 1 week ago

Superseded by #3893.