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Bumps third_party/litex from
95b310e
toc95a6e0
.Commits
c95a6e0
soc/interconnect/stream: Add Delay module.b2f63b3
CHANGES.md: Update.427ec10
CONTRIBUTORS: Update.726d39f
LICENSE: Bump year.baff4c6
Merge pull request #2075 from trabucayre/efinix_clkinput_signal033ec13
Merge pull request #2076 from trabucayre/xc7s_jtag6e9dffd
soc/core/hyperbus: Avoid combinatorial loop on write bursts (Reported when bu...ad2c3fc
soc/cores/cpu/vexiirscv: Add standard variant to allow compilation without sp...f1e1f35
build/efinix/ifacewriter.py: allows the use of ClockSignal for IN_CLK_PIN (gpio)aca959b
build/efinix/common.py: ClkInput: added ClockSignal supportDependabot will resolve any conflicts with this PR as long as you don't alter it yourself. You can also trigger a rebase manually by commenting
@dependabot rebase
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