Open litghost opened 5 years ago
@litghost Regarding "Add a comment above LUT6_2's with the equation form of the LUT from input to output. Ideally they will be reduced equations.":
You mean to write own implementation of an algorithm which converts a truth table with up to 6 inputs to a boolean equation ? Or use an already available solver for this task ? Pure python or an external library/tool ?
I would gladly go with this task, but the only solution I see right now is to use Karnaugh tables related stuff. Or do you have something else on your mind ?
@litghost Regarding "Add a comment above LUT6_2's with the equation form of the LUT from input to output. Ideally they will be reduced equations.":
You mean to write own implementation of an algorithm which converts a truth table with up to 6 inputs to a boolean equation ? Or use an already available solver for this task ? Pure python or an external library/tool ?
Yosys can perform this composition, and I believe there are python libraries too.
I would gladly go with this task, but the only solution I see right now is to use Karnaugh tables related stuff. Or do you have something else on your mind ?
That is what I was thinking, about it doesn't have to be all implemented by us.
@litghost
Yosys can perform this composition
I believe that Yosys can only do the opposite: convert boolean equation to a truth table. Not vice-versa.
I found some implementation of Karnaugh map solvers in python but they are limited to 4 inputs only. We are aiming at LUTs with up to 6 inputs (as they are in 7-series) right? A Karnaugh solver is very straightforward so I can write own implementation for 6-input LUTs.
There is also the Quine-McCluskey algorithm which will always find the optimal solution but it is too much time consuming. AFAIK works for any number of inputs. Implementations are available.
I found also a heuristic algorithm called "Espresso". There is source code available: https://ptolemy.berkeley.edu/projects/embedded/pubs/downloads/espresso/index.htm
I'll keep looking for other solutions. I guess I'll go with this task.
In order to better compare timing information output from VPR and Vivado, it is good to annotate the BEL names with the VPR names. I'll look into improving that next. This should enable side-by-side timing path comparisons.
@mkurc-ant BTW I found the following - Generate logic expressions for all 64K boolean functions of four variables A, B, C, D
# Generate logic expressions for all 64K boolean functions of four variables A, B, C, D # The idea is to start with simple expressions, then take all combinations of these to # generate new expressions, then all combinations of the new expressions, etc. until # everything has been generated. # # Formulas are built up as trees, e.g. ['+', 'A', 'B'] is "A or B"
With https://github.com/SymbiFlow/symbiflow-arch-defs/pull/577, fasm2v is good enough to be useful, however it could be more useful when debugging correctness issues with some more features.
Ideas to improve output, along with difficulty:
So for example:
becomes:
Becomes:
This change leads into the next change:
And then matching the VPR rr graph source node OPIN back into a 7-series source, and then renaming the net. In the example above, the AMUX OPIN at grid location (30,22) should be named $abc$11234$n2115. AMUX OPIN at grid location (30, 20) corresponds the SLICEM located at tile CLBLM_L_X10Y128. So the fasm2verilog name in that case is CLBLM_L_X10Y128_SLICE_X12Y128_AMUX.
Getting back to VPR net names probably is a multi-step process:
{tile}_{site}_{site pin}
. The required map is fasm2verilog net name -> VPR net name.becomes