The utils/vpr_pbtype_to_eblif.py tool currently tries to load a pb_type.xml file and generate a suitable .eblif file for testing the pb_type.xml can be used in VtR. This doesn't work when the pb_type.xml has internal paths which don't get to pins.
Instead we should use Yosys to generate the .eblif file. The process might look like the following;
Load the .sim.v file into Yosys
Get Yosys to write the .eblif file.
Load the .eblif file and work out the number of top level .input and .output signals
Generate a dummy arch.xml file with enough IO pads and one tile which includes the pb_type.xml
The
utils/vpr_pbtype_to_eblif.py
tool currently tries to load apb_type.xml
file and generate a suitable.eblif
file for testing thepb_type.xml
can be used in VtR. This doesn't work when thepb_type.xml
has internal paths which don't get to pins.Instead we should use Yosys to generate the
.eblif
file. The process might look like the following;.sim.v
file into Yosys.eblif
file..eblif
file and work out the number of top level.input
and.output
signalsarch.xml
file with enough IO pads and one tile which includes thepb_type.xml
Step (4) might still make sense to be done as part of
utils/vpr_pbtype_arch_wrapper.py
.