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f4pga / f4pga-arch-defs

FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
https://f4pga.org
ISC License
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Use Yosys on .sim.v files to generate a .eblif needed for architecture testing #746

Open mithro opened 5 years ago

mithro commented 5 years ago

The utils/vpr_pbtype_to_eblif.py tool currently tries to load a pb_type.xml file and generate a suitable .eblif file for testing the pb_type.xml can be used in VtR. This doesn't work when the pb_type.xml has internal paths which don't get to pins.

Instead we should use Yosys to generate the .eblif file. The process might look like the following;

  1. Load the .sim.v file into Yosys
  2. Get Yosys to write the .eblif file.
  3. Load the .eblif file and work out the number of top level .input and .output signals
  4. Generate a dummy arch.xml file with enough IO pads and one tile which includes the pb_type.xml

Step (4) might still make sense to be done as part of utils/vpr_pbtype_arch_wrapper.py.

kgugala commented 5 years ago

this is done in #703