Create a Python library for generating VtR arch.xml file

[mithro]

Currently we generate all the arch.xml files by either;

• Hand using XML includes
• @davesha1's Verilog to arch.xml generator.

As @jhol points out, it would be much easier to generate a lot of the definitions in Python and then dump the XML from that.

This would also make it easier to do the many variations of the testing architectures.

[mithro]

We could also look at migen to generate Verilog from the same structures.

[mithro]

The Verilog to arch generator could use this API too...

[mithro]

@jhol has some examples of how this might work here -> https://github.com/jhol/icestorm/blob/vtr-py/icebox/vtr.py

GitHub

jhol/icestorm

icestorm - Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentaion (Reverse Engineered)

[mridubhatnagar]

Have worked on create an XML, parsing an XML, with Python.

Is this what the issue needs?

[mithro]

Hi @mridubhatnagar,

We want to be able to programmatically generate Verilog to Routing FPGA architecture files. These XML files describe the internals of an FPGA.

We could just use the DOM to do this, but the DOM is not a great Python API. It also sucks if we change from using XML format to some other type of format.

So what we are after is a Python API for creating these FPGA structures and then a way to convert these FPGA structures to and from the XML format.

You can see how @jhol was doing this here and use that as inspiration. You can also see our rr_graph library as inspiration too.

One approach to this would be creating an XML schema for the file format and then auto-generating the Python API from that, see the following examples;

• http://www.davekuhlman.org/generateDS.html
• http://pyxb.sourceforge.net/
• https://github.com/knorby/pyxsd

lxml.de's objectify might be another way to do this.

The first goal would be to easily generate the same architecture files as found in the testarch repository before building up towards being able to generate much more complicated structure.

If you want to chat more, find mithro on the ##openfpga IRC channel or email me at me@mith.ro.

Hope that helps!

generateDS -- Generate Data Structures from XML Schema

PyXB: Python XML Schema Bindings — PyXB 1.2.6 documentation

GitHub

knorby/pyxsd

pyxsd - Python Class Mappings for XML Schema

[mithro]

Also see the related issue here -> https://github.com/SymbiFlow/ideas/issues/4

[mithro]

There is a WIP at https://github.com/leon575777642/vprgen/tree/master/vprgen

GitHub

leon575777642/vprgen

VPR's architecture description and routing resource graph XML generation API - leon575777642/vprgen