Create a Python library for generating VtR arch.xml files

[mithro]

Create a Python library for generating VtR arch.xml files

Brief explanation

Verilog to Routing uses XML files to describe the architecture in an FPGA. This format is described in the Verilog to Routing docs. We need to regularly generate these XML files from Python, so it would be nice to have a good library for doing that.

Expected results

A Python library for generating VtR arch.xml files easily.

[mithro]

There are a number of existing projects which also generate VtR arch.xml files. It would probably be good to checkout;

• The code in SymbiFlow Architecture Definitions.
• https://openfpga.readthedocs.io/en/latest/arch_lang/index.html
• https://prga.readthedocs.io/en/latest/

Maybe others?

Extended Architecture Description Language — OpenFPGA 1.0 documentation

Welcome to the documentation of Princeton Reconfigurable Gate Array! — Princeton Reconfigurable Gate Array 0.1 alpha documentation

[mithro]

You might want to look into auto generating the Python bindings from the XML descriptions. See #4 and https://github.com/SymbiFlow/symbiflow-arch-defs/tree/master/common/xml

GitHub

SymbiFlow/symbiflow-arch-defs

FOSS architecture definitions of FPGA hardware useful for doing PnR device generation. - SymbiFlow/symbiflow-arch-defs

[mithro]

Work on this has started at https://github.com/leon575777642/vprgen and https://github.com/mithro/vprgen

GitHub

leon575777642/vprgen

VPR's architecture description and routing resource graph XML generation API - leon575777642/vprgen

GitHub

mithro/vprgen

VPR's architecture description and routing resource graph XML generation API - mithro/vprgen