Add support EDIF to Verilog to Routing

f4pga / ideas

Random ideas and interesting ideas for things we hope to eventually do.

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Add support EDIF to Verilog to Routing #5

Open mithro opened 6 years ago

mithro commented 6 years ago

Currently Verilog to Routing only support BLIF. BLIF has a whole bunch of limitations, like not supporting names for objects (only nets). No support for parameters, etc.

It would be good to have support EDIF in VPR as an alternative to BLIF.

mithro commented 6 years ago

https://en.wikipedia.org/wiki/EDIF

mithro commented 6 years ago

The EDIF parser could be shared with #6