f4pga / prjuray

Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.
https://prjuray.rtfd.io
Apache License 2.0
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HDIO IO config bits not maching #15

Closed daveshah1 closed 4 years ago

daveshah1 commented 4 years ago

Running the following small Ultra96 design through Vivado 2019.2 (xczu3eg-sbva484-1-i device):

module top(
    output led0,
    output led1
    );

    wire [3:0] plclk;
    PS8 ps8_i(.PLCLK(plclk));

    wire clk;
    BUFG_PS bufg_i (.I(plclk[0]), .O(clk));

    reg [23:0] ctr;

    always @(posedge clk)
        ctr <= ctr + 1'b1;

    assign {led1, led0} = ctr[23:22];
endmodule
set_property PACKAGE_PIN A9 [get_ports led0]
set_property PACKAGE_PIN B9 [get_ports led1]
set_property IOSTANDARD LVCMOS18 [get_ports led0]
set_property IOSTANDARD LVCMOS18 [get_ports led1]

and then running bit2fasm.py --verbose on the bitstream, there are some unknown bits:

# In frame 0x00081e00 12 bits were not converted.
{ unknown_bit = "00081e00_132_3", unknown_segment = "0x00081e00", unknown_segbit = "00_2115" }
{ unknown_bit = "00081e00_134_5", unknown_segment = "0x00081e00", unknown_segbit = "00_2149" }
{ unknown_bit = "00081e00_134_6", unknown_segment = "0x00081e00", unknown_segbit = "00_2150" }
{ unknown_bit = "00081e00_138_3", unknown_segment = "0x00081e00", unknown_segbit = "00_2211" }
{ unknown_bit = "00081e00_134_8", unknown_segment = "0x00081e00", unknown_segbit = "00_2152" }
{ unknown_bit = "00081e00_140_5", unknown_segment = "0x00081e00", unknown_segbit = "00_2245" }
{ unknown_bit = "00081e00_140_6", unknown_segment = "0x00081e00", unknown_segbit = "00_2246" }
{ unknown_bit = "00081e00_140_8", unknown_segment = "0x00081e00", unknown_segbit = "00_2248" }
{ unknown_bit = "00081e00_134_13", unknown_segment = "0x00081e00", unknown_segbit = "00_2157" }
{ unknown_bit = "00081e00_140_13", unknown_segment = "0x00081e00", unknown_segbit = "00_2253" }
{ unknown_bit = "00081e00_139_13", unknown_segment = "0x00081e00", unknown_segbit = "00_2237" }
{ unknown_bit = "00081e00_133_13", unknown_segment = "0x00081e00", unknown_segbit = "00_2141" }

# In frame 0x00081e01 14 bits were not converted.
{ unknown_bit = "00081e01_138_1", unknown_segment = "0x00081e00", unknown_segbit = "01_2209" }
{ unknown_bit = "00081e01_138_2", unknown_segment = "0x00081e00", unknown_segbit = "01_2210" }
{ unknown_bit = "00081e01_138_3", unknown_segment = "0x00081e00", unknown_segbit = "01_2211" }
{ unknown_bit = "00081e01_132_1", unknown_segment = "0x00081e00", unknown_segbit = "01_2113" }
{ unknown_bit = "00081e01_132_2", unknown_segment = "0x00081e00", unknown_segbit = "01_2114" }
{ unknown_bit = "00081e01_132_3", unknown_segment = "0x00081e00", unknown_segbit = "01_2115" }
{ unknown_bit = "00081e01_140_1", unknown_segment = "0x00081e00", unknown_segbit = "01_2241" }
{ unknown_bit = "00081e01_140_5", unknown_segment = "0x00081e00", unknown_segbit = "01_2245" }
{ unknown_bit = "00081e01_140_7", unknown_segment = "0x00081e00", unknown_segbit = "01_2247" }
{ unknown_bit = "00081e01_140_13", unknown_segment = "0x00081e00", unknown_segbit = "01_2253" }
{ unknown_bit = "00081e01_134_1", unknown_segment = "0x00081e00", unknown_segbit = "01_2145" }
{ unknown_bit = "00081e01_134_5", unknown_segment = "0x00081e00", unknown_segbit = "01_2149" }
{ unknown_bit = "00081e01_134_7", unknown_segment = "0x00081e00", unknown_segbit = "01_2151" }
{ unknown_bit = "00081e01_134_13", unknown_segment = "0x00081e00", unknown_segbit = "01_2157" }

It looks like these are the location of the two IO pins in the HDIO_TOP_RIGHT tile, and they are "unknown" because for some reason it isn't matching any of the IO types in the database - I haven't looked into why yet.

litghost commented 4 years ago

Ya, this is related to #5. When I run 031 locally, I usually get a good solution. I think the HDIO IOI bits are sometimes coupling into the IOB solutions.

daveshah1 commented 4 years ago

Can confirm that the issue is solved using the next_zynqusp_db branch of prjuray-db and this example now gives no unknown bits.