search

f4pga / prjuray

Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.
https://prjuray.rtfd.io
Apache License 2.0
71 stars 14 forks source link

XIPHY clock routing bits missing #23

Open daveshah1 opened 4 years ago

daveshah1 commented 4 years ago

The data for RCLK_XIPHY_OUTER_RIGHT is missing the bits for the pips that select the clocks going out to the XIPHYs:

Screenshot from 2020-07-22 14-46-39

This isn't a massive blocker at the moment as the CMT should probably be a bigger priority, but just making sure this isn't forgotten.