Question on case 010_clb_lutinit

f4pga / prjxray

Documenting the Xilinx 7-series bit-stream format.

https://f4pga.github.io/prjxray-db/

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Question on case 010_clb_lutinit #1911

Open KKtiandao opened 2 years ago

KKtiandao commented 2 years ago

I'm researching on principles working on fuzzer cases. But I could not understand top.v.
What are the principles of function "xorshift32/hash32/hash64" ?

What should I take into account when modify top.v or write my own 'top.v'?

KKtiandao commented 2 years ago

@mithro Hi, would you give me some suggestions on how to understand fuzzer cases or how I add a new verilog and ensure cover bits completely?

mithro commented 2 years ago

I'm not sure I understand your question?

KKtiandao commented 2 years ago

@mithro I just want to know how to verify if these fuzz cases like top.v can generate a complete function-bits set.