f4pga / prjxray

Documenting the Xilinx 7-series bit-stream format.
https://f4pga.github.io/prjxray-db/
ISC License
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prjxray-db inconsistent, bits resulting in invalid word addresses (>100) #2300

Open hansfbaier opened 6 months ago

hansfbaier commented 6 months ago

It looks like the prjxray-db is inconsistent, for example in Artix7/Spartan7 there is

    "LIOI3_SING_X0Y149": {
        "bits": {
            "CLB_IO_CLK": {
                "alias": {
                    "sites": {},
                    "start_offset": 0,
                    "type": "LIOI3"
                },
                "baseaddr": "0x00020000",
                "frames": 42,
                "offset": 99,
                "words": 2
            }
        },

Then there are features like:

segbits_lioi3.db:LIOI3.IOI_ILOGIC0_CLK.IOI_LEAF_GCLK0 28_67 28_79 29_74
segbits_lioi3_tbytesrc.db:LIOI3_TBYTESRC.IOI_ILOGIC0_CLK.IOI_LEAF_GCLK0 28_67 28_79 29_74
segbits_lioi3_tbyteterm.db:LIOI3_TBYTETERM.IOI_ILOGIC0_CLK.IOI_LEAF_GCLK0 28_67 28_79 29_74
segbits_rioi3.db:RIOI3.IOI_ILOGIC0_CLK.IOI_LEAF_GCLK0 28_67 28_79 29_74
segbits_rioi3_tbytesrc.db:RIOI3_TBYTESRC.IOI_ILOGIC0_CLK.IOI_LEAF_GCLK0 28_67 28_79 29_74
segbits_rioi3_tbyteterm.db:RIOI3_TBYTETERM.IOI_ILOGIC0_CLK.IOI_LEAF_GCLK0 28_67 28_79 29_74

When these feature are used in the SING tile above, then the corresponding word address is 101: The word address is calculated:

word_addr = bit.word_bit // bitstream.WORD_SIZE_BITS

So in this example bit 28_79 gives word address 99 + 79//32 = 99+2 = 101. But each frame only has 101 words, with word addresses ranging from 0..100 So either the offset is wrong in tilegrid.json, or the bits in those features are wrong.

hansfbaier commented 6 months ago

It looks like the SING tiles have different pips (fuzzers/037-iob-pips) 20240109_02h25m46s_grim

hansfbaier commented 6 months ago

The reason for this is that SING tiles have different switchboxes and their own set of PIPs, which are currently not supported by prjxray image