Closed louisom closed 7 years ago
Linked without user apps got same result
CC user/lib/l4/platform/syscalls.o
CC user/lib/l4/pager.o
CC user/lib/io/l4io.o
CC user/lib/io/user_interrupt.o
CC user/lib/libposix/fork.o
CC user/lib/libposix/pthread.o
LD f9_nosym.elf
NM f9.symmap.o
LD f9.elf
OBJCOPY f9.elf.bin
CAT f9.bin
killall -q qemu-system-arm
make: [mk/generic.mk:94: qemu] Error 1 (ignored)
../qemu_stm32/arm-softmmu/qemu-system-arm -M stm32-p103 -kernel build/stm32p103/f9.bin -serial stdio -semihosting
(process:7715): GLib-WARNING **: gmem.c:483: custom memory allocation vtable not supported
STM32_UART: UART1 clock is set to 0 Hz.
STM32_UART: UART1 BRR set to 0.
STM32_UART: UART1 Baud is set to 0 bits per sec.
STM32_UART: UART2 clock is set to 0 Hz.
STM32_UART: UART2 BRR set to 0.
STM32_UART: UART2 Baud is set to 0 bits per sec.
STM32_UART: UART3 clock is set to 0 Hz.
STM32_UART: UART3 BRR set to 0.
STM32_UART: UART3 Baud is set to 0 bits per sec.
STM32_UART: UART4 clock is set to 0 Hz.
STM32_UART: UART4 BRR set to 0.
STM32_UART: UART4 Baud is set to 0 bits per sec.
STM32_UART: UART5 clock is set to 0 Hz.
STM32_UART: UART5 BRR set to 0.
STM32_UART: UART5 Baud is set to 0 bits per sec.
STM32_UART: UART5 clock is set to 0 Hz.
STM32_UART: UART5 BRR set to 0.
STM32_UART: UART5 Baud is set to 0 bits per sec.
STM32_UART: UART4 clock is set to 0 Hz.
STM32_UART: UART4 BRR set to 0.
STM32_UART: UART4 Baud is set to 0 bits per sec.
STM32_UART: UART3 clock is set to 0 Hz.
STM32_UART: UART3 BRR set to 0.
STM32_UART: UART3 Baud is set to 0 bits per sec.
STM32_UART: UART2 clock is set to 0 Hz.
STM32_UART: UART2 BRR set to 0.
STM32_UART: UART2 Baud is set to 0 bits per sec.
STM32_UART: UART1 clock is set to 0 Hz.
STM32_UART: UART1 BRR set to 0.
STM32_UART: UART1 Baud is set to 0 bits per sec.
LED Off
CLKTREE: HSI Output Change (SrcClk:None InFreq:8000000 OutFreq:8000000 Mul:1 Div:1 Enabled:1)
CLKTREE: HSI/2 Output Change (SrcClk:HSI InFreq:8000000 OutFreq:4000000 Mul:1 Div:2 Enabled:1)
CLKTREE: SYSCLK Output Change (SrcClk:HSI InFreq:8000000 OutFreq:8000000 Mul:1 Div:1 Enabled:1)
CLKTREE: HCLK Output Change (SrcClk:SYSCLK InFreq:8000000 OutFreq:8000000 Mul:1 Div:1 Enabled:1)
STM32_RCC: Cortex SYSTICK frequency set to 8000000 Hz (scale set to 125).
STM32_RCC: Cortex SYSTICK ext ref frequency set to 1000000 Hz (scale set to 1000).
CLKTREE: PCLK1 Output Change (SrcClk:HCLK InFreq:8000000 OutFreq:8000000 Mul:1 Div:1 Enabled:1)
CLKTREE: PCLK2 Output Change (SrcClk:HCLK InFreq:8000000 OutFreq:8000000 Mul:1 Div:1 Enabled:1)
CLKTREE: HSE Output Change (SrcClk:None InFreq:8000000 OutFreq:8000000 Mul:1 Div:1 Enabled:1)
CLKTREE: HSE/2 Output Change (SrcClk:HSE InFreq:8000000 OutFreq:4000000 Mul:1 Div:2 Enabled:1)
CLKTREE: PLLXTPRE Output Change (SrcClk:HSE InFreq:8000000 OutFreq:8000000 Mul:1 Div:1 Enabled:1)
CLKTREE: PCLK2 Output Change (SrcClk:HCLK InFreq:8000000 OutFreq:4000000 Mul:1 Div:2 Enabled:1)
CLKTREE: PCLK1 Output Change (SrcClk:HCLK InFreq:8000000 OutFreq:2000000 Mul:1 Div:4 Enabled:1)
CLKTREE: PLLCLK Output Change (SrcClk:HSI/2 InFreq:4000000 OutFreq:32000000 Mul:8 Div:1 Enabled:1)
CLKTREE: SYSCLK Output Change (SrcClk:PLLCLK InFreq:32000000 OutFreq:32000000 Mul:1 Div:1 Enabled:1)
CLKTREE: HCLK Output Change (SrcClk:SYSCLK InFreq:32000000 OutFreq:32000000 Mul:1 Div:1 Enabled:1)
STM32_RCC: Cortex SYSTICK frequency set to 32000000 Hz (scale set to 31).
STM32_RCC: Cortex SYSTICK ext ref frequency set to 4000000 Hz (scale set to 250).
CLKTREE: PCLK1 Output Change (SrcClk:HCLK InFreq:32000000 OutFreq:8000000 Mul:1 Div:4 Enabled:1)
CLKTREE: PCLK2 Output Change (SrcClk:HCLK InFreq:32000000 OutFreq:16000000 Mul:1 Div:2 Enabled:1)
CLKTREE: UART2 Output Change (SrcClk:PCLK1 InFreq:8000000 OutFreq:8000000 Mul:1 Div:1 Enabled:1)
STM32_UART: UART2 clock is set to 8000000 Hz.
STM32_UART: UART2 BRR set to 0.
STM32_UART: UART2 Baud is set to 0 bits per sec.
CLKTREE: GPIOA Output Change (SrcClk:PCLK2 InFreq:16000000 OutFreq:16000000 Mul:1 Div:1 Enabled:1)
STM32_UART: UART2 clock is set to 8000000 Hz.
STM32_UART: UART2 BRR set to 364.
STM32_UART: UART2 Baud is set to 21978 bits per sec.
Reached end of schedule()
-------KTABLES------
-------KTIMER------
ktimer events:
EVENT DELTA
-------NOW------
Now is 0
-------SOFTIRQ------
Kernel timer events not scheduled
Asynchronous events not scheduled
System calls not scheduled
KDB enters not scheduled
-------THREADS------
type global local state parent
-------MEMPOOLS------
NAME SIZE [START :END ] FLAGS
KTEXT 19340 [08001000:08005b8c] r-x --- N
UTEXT 1536 [2000f200:2000f800] --- r-x M
KIP 512 [20000400:20000600] rw- r-- S
KDATA 911 [20000600:2000098f] rw- --- N
KBSS 59312 [20000a00:2000f1b0] rw- --- N
UDATA 768 [2000f800:2000fb00] --- rw- M
UBSS 0 [2000fb00:2000fb00] --- rw- M
MEM0 50376 [2000fb38:2001c000] --- rw- S
KBITMAP 56 [2000fb00:2000fb38] rw- --- N
APB1DEV 30720 [40000000:40007800] --- rw- D
APB2_1DEV 19456 [40010000:40014c00] --- rw- D
APB2_2DEV 3072 [40014000:40014c00] --- rw- D
AHB1_1DEV 15360 [40020000:40023c00] --- rw- D
AHB1_2DEV 115712 [40023c00:40040000] --- rw- D
AHB2DEV 397312 [50000000:50061000] --- rw- D
AHB3DEV 1073745920 [60000000:a0001000] --- rw- D
-------AS------
-------TOP------
Init sampling...
Stack dump:
20000338 200013b0 08003f0f 08005730 000020ac 00000001 00000000 0000202c
0000000c 20000618 080057c5 200003e8 08001677 fffffff9 40004400 000020ac
00000001 0000202c 00000006 0800182f 0800148c 01000200 00000000 0000000d
080017f1 00000000 00000000 080015b7 0000000a 08002035 00000020 00000020
00000000 0000e7b0 00000000 00000000 00000000 00000000 00000000 00000000
00000000 08001ed9 080015fd 200003e4 0000e7b0 08004059 080057c4 200007d8
00000000 20001380 e000ed24 080040f5 00000000 00000000 00000000
Root cause in #127
Using QEMU-stm32 to run stm32p103, got reached end of schedule()
using default config file. with arm-none-eabi-gcc version 6.2.0 (I've check this version toolchain can work on stm32f429)