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f9micro / f9-kernel

An efficient and secure microkernel built for ARM Cortex-M cores, inspired by L4
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lr value is incorrect when floating point support is enabled #9

Closed georgekang closed 11 years ago

georgekang commented 11 years ago

When floating point support is enabled, lr value would be strange (0xffffffe9) in IRQ_HANDLER, and we need to save ctx's lr in irq_save routine in order to correct it.

We might have to implement proper FPU initialization and corresponding support for ARM Cortex-M4F.

jserv commented 11 years ago

To be more precise, the original workaround @georgekang mentioned as following commit 8860fbd removed:

--- a/include/platform/irq.h
+++ b/include/platform/irq.h
@@ -51,7 +51,6 @@ static inline int irq_number()
  */
 #define irq_save(ctx) \
        __asm__ __volatile__ ("cpsid i");                               \
-       __asm__ __volatile__ ("mov lr, %0" : : "r" ((ctx)->ret));       \
        __asm__ __volatile__ ("mov r0, %0" : : "r" ((ctx)->regs));      \
        __asm__ __volatile__ ("stm r0, {r4-r11}");                      \
        __asm__ __volatile__ ("cmp lr, #0xFFFFFFF9");                   \
arcbbb commented 11 years ago

If it's all about which stack to choose while returning from handler, will it solve this issue with and r1, lr, #4 instead of cmp lr, #0xFFFFFFF9?

--- a/include/platform/irq.h
+++ b/include/platform/irq.h
@@ -54,7 +54,8 @@ static inline int irq_number()
        __asm__ __volatile__ ("mov lr, %0" : : "r" ((ctx)->ret));       \
        __asm__ __volatile__ ("mov r0, %0" : : "r" ((ctx)->regs));      \
        __asm__ __volatile__ ("stm r0, {r4-r11}");                      \
-       __asm__ __volatile__ ("cmp lr, #0xFFFFFFF9");                   \
+       __asm__ __volatile__ ("and r1, lr, #4");                        \
+       __asm__ __volatile__ ("cmp r1, #0");                            \
        __asm__ __volatile__ ("ite eq");                                \
        __asm__ __volatile__ ("mrseq r0, msp");                         \
        __asm__ __volatile__ ("mrsne r0, psp");                         \
@@ -64,7 +65,8 @@ static inline int irq_number()
        __asm__ __volatile__ ("mov lr, %0" : : "r" ((ctx)->ret));       \
        __asm__ __volatile__ ("mov r0, %0" : : "r" ((ctx)->sp));        \
        __asm__ __volatile__ ("mov r2, %0" : : "r" ((ctx)->ctl));       \
-       __asm__ __volatile__ ("cmp lr, #0xFFFFFFF9");                   \
+       __asm__ __volatile__ ("and r1, lr, #4");                        \
+       __asm__ __volatile__ ("cmp r1, #0");                            \
        __asm__ __volatile__ ("ite eq");                                \
        __asm__ __volatile__ ("msreq msp, r0");                         \
        __asm__ __volatile__ ("msrne psp, r0");                         \
jserv commented 11 years ago

FPU initialization is considered as the root cause, and it is already supported by other systems such as RT-Thread:

jserv commented 11 years ago

FPU related implementation of RT-Thread: cortex-m4

jserv commented 11 years ago

Per discussions with @georgekang, we would likely merge PendSV specific handling from @arcbbb first, and then we will implement FPU hook inside context switching.

arcbbb commented 11 years ago

Here is the rebased PendSV handling patch: 672e292

georgekang commented 11 years ago

WIP in 2eac42fa43d33409cbe7edaab58ec84063c7d9df

georgekang commented 11 years ago

Update by jserv's suggestion. 16d021e948a8d4740bde486c411dfb85fec54066