Add Yosys's RTLIL input/output

[programmerjake]

Yosys is currently the de-facto standard implementation for open-source synthesis (we're currently using it along with nmigen to build a completely open-source Power/RISC-V SoC with CPU/GPU/VPU).

Add support for converting to/from Yosys's intermediate representation.

Adding support for RTLIL would allow using Yosys to convert LLHD to Verilog, implementing #53

Related to #63

[fabianschuiki]

This is an excellent suggestion, especially since it helps to tie in LLHD with the existing ecosystem. Adding this to the planned v0.14 features.

Some links for impl. reference:

• rtlil.h
• Yosys Manual
• ilang_parser.y
• ilang_lexer.l

[xhebox]

I am long for a consistent SSA IR for HDL. And today I accidentally found the paper and your work, impressive. :)

The problem is that this project is not practical yet. We clearly need to integrate with other EDA tools. So any progress on this issue? Although I am new to rust and HDL, I want to contribute to this issue.

[fabianschuiki]

Not yet, spare time is currently scarce, so thinks move a bit slower. The place to start would be in src/bin/llhd-conv, where we would add a separate reader/writer for RTLIL, and run the translation from an LLHD graph to RTLIL, and vice versa. This likely requires some transformations along the way, to map unsupported features.

[xhebox]

Just a progress report. I have a hard time on learning rust. And I've contributed lots of my time on TiDB... So far, I just have made a rtlil parser. I will upload it as a crate/lib to my github this week... Rtlil ast to "text" is also easy to support. So, this parser should enable the work on the implementation of mapping between llhd/rtlil.

[fabianschuiki]

I will upload it as a crate/lib to my github this week [...]. So, this parser should enable the work on the implementation of mapping between llhd/rtlil.

Cool, looking forward to this!

[xhebox]

It is uploaded to 'xhebox/rtlil-rs', with support of rewriting to text. An example parser/rewriter is located at bin/parse.rs. I haven't written any test yet.

EDIT: I will concentrate on completing the parser project for some time. Anyone who interested can start the work on this issue earlier. The api is not likely to change too much.

[dvc94ch]

@xhebox any progress? would really like to use moore/llhd as a yosys system verilog frontend

[xhebox]

@dvc94ch nope. I am busy on other things recently. I have uploaded the parser, but I did not start the worker of converter.

[NotAFile]

Since I am somewhat familiar with yosys internals and moore looked exciting to me, I thought I'd take a look at the LLHD spec to see how easy it would be to do this.

I unfortunately have to conclude that converting llhd to RTLIL is going to be a challenge to say the least. While a list of instructions and basic blocks are great for simulating on a CPU, they are far less suited to targeting real hardware, which for most IRs is represented as a netlist and/or list of atomic rules.

Turning basic blocks into a netlist is a notoriously difficult problem (a subset of High Level Synthesis) and a far harder problem than converting Verilog or VHDL to the likes of RTLIL directly due to the amount of information that needs to be re-derived.

So realistically, the only options I see here are either emitting RTLIL from moore directly or augmenting llhd's CPU-optimized units with ones optimized for generating hardware.

[fabianschuiki]

Hey @NotAFile, thanks for taking a closer look at this! LLHD intends to capture the exact semantics of Verilog and VHDL, and then offer a simpler abstraction to ingest in other tools. So in a sense, when you build a tool like Yosys, and you read in Verilog, you have to somehow deal with always blocks, conditionals, and all that other sequential programming style of representing hardware. From that you'd generate the RTLIL representation in a more structure way. LLHD targets exactly this niche, but instead of having to look at always blocks and ifs and what not, it provides a much simpler representation -- basic blocks and control flow among them -- for which there is a large corpus of prior art in the compiler community. LLHD doesn't try to directly present a netlist of registers and combinational gates, but rather a precursor that is easily transformed into such a list. The benefit is that when you go from LLHD to RTLIL instead of SV to RTLIL, people can come in and offer new ways to lower SV to an equivalent LLHD representation (for example making classes partially synthesizable) which Yosys would benefit from without having to do the work on its own.

[NotAFile]

Hi @fabianschuiki, thanks for your explanation. I'm still concerned about the feasibility of targeting non-simulators with the current spec, but I'll keep an eye on the project and take another look once it gets to the point of having some examples of turning it into hardware.