fabianschuiki
commented
4 years ago Hi @tampler
I'm interested in this project, since am working on a commercial version of a FIRRTL Simulator implemented in Scala for large SoC designs. Our goal is to support Rocket and Boom simulations in pure FIRRTL first, and then add SV. VHDL is not considered at all for a 2y roadmap.
That's an awesome endeavor!
We work to promote Chisel as the first class language for simulation and synthesis, which is kind of what you mentioned as a "future" in your paper.
We indeed developed our own IR, frontend parser, and a sim backend implementation, which is capable for massive parallelization and cluster simulation, kudos to JVM Ecosystem.
However, I see no value in building and supporting my own IR and would happily switch to LLHD or similar. I'm also looking at
LGraphIR to be compatible withYosysandSTAtools.
Indeed, one way of how LLHD can be useful is to have languages like Chisel/FIRRTL map to it rather than Verilog. Of course if you already use LGraph to push designs through other tools, then changing to LLHD might not be worthwhile just for the sake of changing.
Currently, we stuck to FIRRTL, since Berkeley added many useful passes on the FIRRTL level, including early area, timing and power estimation, DFT insertion, FPGA cluster simulation support, etc. More info about that here and here. The later paper shows excellent results for integration with
Yosysand combining both FIRRTL and Yosys passes to gain a higher level of design optimization.
Yes this is indeed a very nice feat!
- I'm curious about your thoughts on integration LLHD with Chisel and LGraph compatible tools
- LLHD is intended to make it easy to transport designs around. One thing on the todo list is conversion from/to FIRRTL, which would allow for the chain Chisel -> FIRRTL -> LLHD, but also SystemVerilog -> LLHD -> FIRRTL. (https://github.com/fabianschuiki/llhd/issues/124)
- Regarding Yosys specifically, conversion to/from RTLIL is on the todo list (https://github.com/fabianschuiki/llhd/issues/116). Ideally, Yosys will eventually gain a native LLHD frontend, which would allow it to ingest any other HDL that has LLHD support.
- Conversion from/to LGraph would be another step in this direction.
- I'm also interested in a roadmap of
mooreand what are your plans and priorities on it?
The long-term plans are to make this a complete SV implementation (famous last words). In the short-term, I push towards getting the various pulp-platform IPs to compile. At the same time, I'm trying to improve the sv-tests track record of moore.
- Do you consider porting
mooredesign to Scala ?
Not at all.
tampler
Hello
I'm interested in this project, since am working on a commercial version of a FIRRTL Simulator implemented in Scala for large SoC designs. Our goal is to support Rocket and Boom simulations in pure FIRRTL first, and then add SV. VHDL is not considered at all for a 2y roadmap.
We work to promote Chisel as the first class language for simulation and synthesis, which is kind of what you mentioned as a "future" in your paper.
We indeed developed our own IR, frontend parser, and a sim backend implementation, which is capable for massive parallelization and cluster simulation, kudos to JVM Ecosystem.
However, I see no value in building and supporting my own IR and would happily switch to LLHD or similar. I'm also looking at
LGraphIR to be compatible withYosysandSTAtools.Currently, we stuck to FIRRTL, since Berkeley added many useful passes on the FIRRTL level, including early area, timing and power estimation, DFT insertion, FPGA cluster simulation support, etc. More info about that here and here. The later paper shows excellent results for integration with
Yosysand combining both FIRRTL and Yosys passes to gain a higher level of design optimization.So
mooreand what are your plans and priorities on it?mooredesign to Scala ?Sincerely, Boris