Unexpected error: "value is not constant"

[maerhart]

There seems to be an issure in moore when initializing a bit value with an existing wire. The following error is raised:

error: value is not constant
  --> acc-lowered-verilog.sv:15:21-23:
   | 
   |     bit [31:0] _5 = _4;
   |                     ^^ 

when trying to compile the following example:

module _acc_always_ff_45_0(input bit  _0, input bit [31:0] _1, output bit [31:0] _2);
    always@(posedge _0) begin
        _2 <= #(1ns) _1;
    end
endmodule
module _acc_always_comb_82_0(input bit [31:0] _0, input bit [31:0] _1, input bit [31:0] _2, output bit [31:0] _3);
    wire [31:0] _4 = 32'd0;
    wire [31:0] _5 = (_1 != _4) ? (_2 + _0) : _2;
    always@(*) begin
        _3 <= #(2ns) _5;
    end
endmodule
module _acc(input bit  _0, input bit [31:0] _1, input bit [31:0] _2, output bit [31:0] _3);
    wire [31:0] _4 = 32'd0;
    bit [31:0] _5 = _4;
    _acc_always_ff_45_0 inst_0 (_0, _5, _3);
    _acc_always_comb_82_0 inst_1 (_1, _2, _3, _5);
endmodule

This happens for every instance of this pattern. Just let me know if you need more such examples.

Here another snippet:

module _stream_delay(input _0);
    wire [1:0] _1 = 2'd1;
    wire [1:0] _2 = _0 ? 2'd0 : _1;
endmodule

throwing

error: value is not constant
  --> ../verilogfiles/test.sv:3:21-23:
   | 
   |     wire [1:0] _2 = _0 ? 2'd0 : _1;
   |                     ^^             

error: value is not constant
  --> ../verilogfiles/test.sv:3:33-35:
   | 
   |     wire [1:0] _2 = _0 ? 2'd0 : _1;
   |                                 ^^