module A;
wire [31:0] x;
wire y;
B system_bus_xbar (.x(x), .y(y));
endmodule
module B (input [31:0] x, output y);
endmodule
Triggers this compiler bug with moore /tmp/small_case.sv -e A:
compiler bug: lvalue lowering of cast to `logic [31:0]` not yet supported: Range([31:0], false)
--> /tmp/small_case.sv:4:32-33:
|
| B system_bus_xbar (.x(x), .y(y));
| ^
= note: Encountered at src/svlog/mir/lower/lvalue.rs:310
Suspiciously, the logic [31:0] seems to get inherited from the port definition of x. Likely the carry logic for port evaluation accidentally carries the type of x over to y. This looks like it could be related to #223.
This code:
Triggers this compiler bug with
moore /tmp/small_case.sv -e A:Suspiciously, the
logic [31:0]seems to get inherited from the port definition of x. Likely the carry logic for port evaluation accidentally carries the type of x over to y. This looks like it could be related to #223.