Instantiating a module without providing a corresponding module ... definition currently triggers a compiler error. However, it is quite common in Verilog to have extern modules by simply not providing a definition. Moore should provide an option to treat some or all of the undefined modules as external, and infer the types of its ports from the connected signals (as is commonly done). This might combine well with an implementation for the extern module construct of SV. The resulting LLHD should then contain corresponding module declarations.
Instantiating a module without providing a corresponding
module ...definition currently triggers a compiler error. However, it is quite common in Verilog to have extern modules by simply not providing a definition. Moore should provide an option to treat some or all of the undefined modules as external, and infer the types of its ports from the connected signals (as is commonly done). This might combine well with an implementation for theextern moduleconstruct of SV. The resulting LLHD should then contain corresponding module declarations.