Closed eerpini closed 1 year ago
@srikrishnagopu has imported this pull request. If you are a Meta employee, you can view this diff on Phabricator.
@srikrishnagopu merged this pull request in facebook/fboss@f91f9636cb7e56f3a1be3c0d7c126f36de10e24f.
Adding 4 ports on each core other than recycle port (earlier we only had two ports on core1). Refactored the port numbering to be sequential across cores and for the PHY cores to be assigned sequentially on each core.