fair-acc / gr-digitizers

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Add Timing Receiver (Simulation) #117

Closed frankosterfeld closed 1 year ago

frankosterfeld commented 1 year ago

Implements fair-acc/opendigitizer#31

frankosterfeld commented 1 year ago

@RalphSteinhagen Before I continue, can you check if that is roughly what you had in mind, for the WR Receiver?

frankosterfeld commented 1 year ago

Also implements now fair-acc/opendigitizer#28 (without the signal tag though) and fair/opendigitizer#32.

So both the timing receiver simulator (UDP/ZeroMQ) and the usage of the timing messages in the digitizers.

alexxcons commented 1 year ago

A general worry: In the past it happened that e.g. a timing event was received while a trigger for it was missed, leading to a continuous mismatch of timing-messages to the wrong triggers. E.g. imagine timing events which are too close together to be measured as separate triggers, or e.g. timing receiver and digitizer not starting in sync, one of them missing the first event.

That was the reason why I introduced event-matching by timestamp years ago (which as well has its quirks and as well is suboptimal)

Do you plan to implement a way to detect such possible miss-alignments ? E.g. some 'sync procedure', or maybe a variation in the trigger-aplitude for some events to make sure the right trigger is matched to the right timing-message ?