I was running the sample code found on https://github.com/fastmachinelearning/hls4ml-tutorial, and the following error occured. The spec of my setup are the following:
OS ;Ubuntu 18.04.2
Vivado hls4ml 2019.2
python 3.9
C SIMULATION RESULT:
INFO: [SIM 2] CSIM start
INFO: [SIM 4] CSIM will launch GCC as the compiler.
make: 'csim.exe' is up to date.
INFO: Unable to open input/predictions file, using default input.
0.0302734 0.799805 0.0576172 0.147461 0.0390625
INFO: Saved inference results to file: tb_data/csim_results.log
INFO: [SIM 1] CSim done with 0 errors.
INFO: [SIM 3] CSIM finish
SYNTHESIS REPORT:
== Vivado HLS Report for 'myproject'
Date: Fri Jul 5 17:34:39 2024
Version: 2019.2 (Build 2704478 on Wed Nov 06 22:10:23 MST 2019)
I was running the sample code found on https://github.com/fastmachinelearning/hls4ml-tutorial, and the following error occured. The spec of my setup are the following: OS ;Ubuntu 18.04.2 Vivado hls4ml 2019.2 python 3.9
Why co-simulation not found? Can someone help.
I have added the last portion of my output.
INFO: [HLS 200-42] -- Implementing module 'dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SCHED 204-11] Starting scheduling ... INFO: [SCHED 204-61] Pipelining function 'dense_latency.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.'. INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [SCHED 204-11] Finished scheduling. INFO: [HLS 200-111] Elapsed time: 260.08 seconds; current allocated memory: 430.198 MB. INFO: [BIND 205-100] Starting micro-architecture generation ... INFO: [BIND 205-101] Performing variable lifetime analysis. INFO: [BIND 205-101] Exploring resource sharing. INFO: [BIND 205-101] Binding ... INFO: [BIND 205-100] Starting global binding ... INFO: [BIND 205-100] Finished micro-architecture generation. INFO: [HLS 200-111] Elapsed time: 10.79 seconds; current allocated memory: 503.324 MB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-42] -- Implementing module 'relu_ap_fixed_16_6_5_3_0_ap_fixed_16_6_5_3_0_relu_config3_s' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SCHED 204-11] Starting scheduling ... INFO: [SCHED 204-61] Pipelining function 'relu<ap_fixed<16, 6, 5, 3, 0>, ap_fixed<16, 6, 5, 3, 0>, relu_config3>'. INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 1. INFO: [SCHED 204-11] Finished scheduling. INFO: [HLS 200-111] Elapsed time: 6.99 seconds; current allocated memory: 506.867 MB. INFO: [BIND 205-100] Starting micro-architecture generation ... INFO: [BIND 205-101] Performing variable lifetime analysis. INFO: [BIND 205-101] Exploring resource sharing. INFO: [BIND 205-101] Binding ... INFO: [BIND 205-100] Finished micro-architecture generation. INFO: [HLS 200-111] Elapsed time: 0.62 seconds; current allocated memory: 508.371 MB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-42] -- Implementing module 'dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SCHED 204-11] Starting scheduling ... INFO: [SCHED 204-61] Pipelining function 'dense_latency.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.1'. INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [SCHED 204-11] Finished scheduling. INFO: [HLS 200-111] Elapsed time: 6.03 seconds; current allocated memory: 536.746 MB. INFO: [BIND 205-100] Starting micro-architecture generation ... INFO: [BIND 205-101] Performing variable lifetime analysis. INFO: [BIND 205-101] Exploring resource sharing. INFO: [BIND 205-101] Binding ... INFO: [BIND 205-100] Starting global binding ... INFO: [BIND 205-100] Finished micro-architecture generation. INFO: [HLS 200-111] Elapsed time: 36.55 seconds; current allocated memory: 616.398 MB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-42] -- Implementing module 'relu_ap_fixed_16_6_5_3_0_ap_fixed_16_6_5_3_0_relu_config5_s' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SCHED 204-11] Starting scheduling ... INFO: [SCHED 204-61] Pipelining function 'relu<ap_fixed<16, 6, 5, 3, 0>, ap_fixed<16, 6, 5, 3, 0>, relu_config5>'. INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 1. INFO: [SCHED 204-11] Finished scheduling. INFO: [HLS 200-111] Elapsed time: 16.48 seconds; current allocated memory: 621.579 MB. INFO: [BIND 205-100] Starting micro-architecture generation ... INFO: [BIND 205-101] Performing variable lifetime analysis. INFO: [BIND 205-101] Exploring resource sharing. INFO: [BIND 205-101] Binding ... INFO: [BIND 205-100] Finished micro-architecture generation. INFO: [HLS 200-111] Elapsed time: 0.32 seconds; current allocated memory: 622.325 MB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-42] -- Implementing module 'dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SCHED 204-11] Starting scheduling ... INFO: [SCHED 204-61] Pipelining function 'dense_latency.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0'. INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [SCHED 204-11] Finished scheduling. INFO: [HLS 200-111] Elapsed time: 2.94 seconds; current allocated memory: 636.112 MB. INFO: [BIND 205-100] Starting micro-architecture generation ... INFO: [BIND 205-101] Performing variable lifetime analysis. INFO: [BIND 205-101] Exploring resource sharing. INFO: [BIND 205-101] Binding ... INFO: [BIND 205-100] Starting global binding ... INFO: [BIND 205-100] Finished micro-architecture generation. INFO: [HLS 200-111] Elapsed time: 12.28 seconds; current allocated memory: 715.576 MB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-42] -- Implementing module 'relu_ap_fixed_16_6_5_3_0_ap_fixed_16_6_5_3_0_relu_config7_s' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SCHED 204-11] Starting scheduling ... INFO: [SCHED 204-61] Pipelining function 'relu<ap_fixed<16, 6, 5, 3, 0>, ap_fixed<16, 6, 5, 3, 0>, relu_config7>'. INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 1. INFO: [SCHED 204-11] Finished scheduling. INFO: [HLS 200-111] Elapsed time: 8.24 seconds; current allocated memory: 718.534 MB. INFO: [BIND 205-100] Starting micro-architecture generation ... INFO: [BIND 205-101] Performing variable lifetime analysis. INFO: [BIND 205-101] Exploring resource sharing. INFO: [BIND 205-101] Binding ... INFO: [BIND 205-100] Finished micro-architecture generation. INFO: [HLS 200-111] Elapsed time: 0.32 seconds; current allocated memory: 719.281 MB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-42] -- Implementing module 'dense_latency_ap_fixed_ap_fixed_16_6_5_3_0_config8_0_0_0_0_0_0' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SCHED 204-11] Starting scheduling ... INFO: [SCHED 204-61] Pipelining function 'dense_latency<ap_fixed,ap_fixed<16,6,5,3,0>,config8>.0.0.0.0.0.0'. INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [SCHED 204-11] Finished scheduling. INFO: [HLS 200-111] Elapsed time: 0.72 seconds; current allocated memory: 721.840 MB. INFO: [BIND 205-100] Starting micro-architecture generation ... INFO: [BIND 205-101] Performing variable lifetime analysis. INFO: [BIND 205-101] Exploring resource sharing. INFO: [BIND 205-101] Binding ... INFO: [BIND 205-100] Starting global binding ... INFO: [BIND 205-100] Finished micro-architecture generation. INFO: [HLS 200-111] Elapsed time: 1.48 seconds; current allocated memory: 726.397 MB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-42] -- Implementing module 'softmax_stable_ap_fixed_ap_fixed_16_6_5_3_0_softmax_config9_s' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SCHED 204-11] Starting scheduling ... INFO: [SCHED 204-61] Pipelining function 'softmax_stable<ap_fixed,ap_fixed<16,6,5,3,0>,softmax_config9>'. INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 5. INFO: [SCHED 204-11] Finished scheduling. INFO: [HLS 200-111] Elapsed time: 1.46 seconds; current allocated memory: 727.396 MB. INFO: [BIND 205-100] Starting micro-architecture generation ... INFO: [BIND 205-101] Performing variable lifetime analysis. INFO: [BIND 205-101] Exploring resource sharing. INFO: [BIND 205-101] Binding ... INFO: [BIND 205-100] Finished micro-architecture generation. INFO: [HLS 200-111] Elapsed time: 0.3 seconds; current allocated memory: 727.998 MB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-42] -- Implementing module 'myproject' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SCHED 204-11] Starting scheduling ... INFO: [SCHED 204-61] Pipelining function 'myproject'. INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 14. INFO: [SCHED 204-11] Finished scheduling. INFO: [HLS 200-111] Elapsed time: 0.4 seconds; current allocated memory: 728.779 MB. INFO: [BIND 205-100] Starting micro-architecture generation ... INFO: [BIND 205-101] Performing variable lifetime analysis. INFO: [BIND 205-101] Exploring resource sharing. INFO: [BIND 205-101] Binding ... INFO: [BIND 205-100] Finished micro-architecture generation. INFO: [HLS 200-111] Elapsed time: 10.84 seconds; current allocated memory: 745.543 MB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Generating RTL for module 'dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [RTGEN 206-104] Estimated max fanout for 'dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s' is 14096 from HDL expression: (1'b0 == ap_block_pp0_stage0) INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s'. INFO: [HLS 200-111] Elapsed time: 6.66 seconds; current allocated memory: 787.382 MB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Generating RTL for module 'relu_ap_fixed_16_6_5_3_0_ap_fixed_16_6_5_3_0_relu_config3_s' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_ap_fixed_16_6_5_3_0_ap_fixed_16_6_5_3_0_relu_config3_s'. INFO: [HLS 200-111] Elapsed time: 11.03 seconds; current allocated memory: 862.080 MB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Generating RTL for module 'dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [RTGEN 206-104] Estimated max fanout for 'dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1' is 35936 from HDL expression: (1'b0 == ap_block_pp0_stage0) INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1'. INFO: [HLS 200-111] Elapsed time: 2.47 seconds; current allocated memory: 923.258 MB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Generating RTL for module 'relu_ap_fixed_16_6_5_3_0_ap_fixed_16_6_5_3_0_relu_config5_s' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_ap_fixed_16_6_5_3_0_ap_fixed_16_6_5_3_0_relu_config5_s'. INFO: [HLS 200-111] Elapsed time: 27.32 seconds; current allocated memory: 1.043 GB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Generating RTL for module 'dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [RTGEN 206-104] Estimated max fanout for 'dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0' is 18736 from HDL expression: (1'b0 == ap_block_pp0_stage0) INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0'. INFO: [HLS 200-111] Elapsed time: 2.71 seconds; current allocated memory: 1.073 GB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Generating RTL for module 'relu_ap_fixed_16_6_5_3_0_ap_fixed_16_6_5_3_0_relu_config7_s' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [RTGEN 206-100] Finished creating RTL model for 'relu_ap_fixed_16_6_5_3_0_ap_fixed_16_6_5_3_0_relu_config7_s'. INFO: [HLS 200-111] Elapsed time: 13.95 seconds; current allocated memory: 1.143 GB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Generating RTL for module 'dense_latency_ap_fixed_ap_fixed_16_6_5_3_0_config8_0_0_0_0_0_0' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [RTGEN 206-100] Finished creating RTL model for 'dense_latency_ap_fixed_ap_fixed_16_6_5_3_0_config8_0_0_0_0_0_0'. INFO: [HLS 200-111] Elapsed time: 3.03 seconds; current allocated memory: 1.150 GB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Generating RTL for module 'softmax_stable_ap_fixed_ap_fixed_16_6_5_3_0_softmax_config9_s' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [RTGEN 206-100] Generating core module 'myproject_mul_mul_18s_17ns_26_1_1': 5 instance(s). INFO: [RTGEN 206-100] Finished creating RTL model for 'softmax_stable_ap_fixed_ap_fixed_16_6_5_3_0_softmax_config9_s'. INFO: [HLS 200-111] Elapsed time: 4.58 seconds; current allocated memory: 1.163 GB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Generating RTL for module 'myproject' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [RTGEN 206-500] Setting interface mode on port 'myproject/input_1_V' to 'ap_vld'. INFO: [RTGEN 206-500] Setting interface mode on port 'myproject/layer9_out_0_V' to 'ap_vld'. INFO: [RTGEN 206-500] Setting interface mode on port 'myproject/layer9_out_1_V' to 'ap_vld'. INFO: [RTGEN 206-500] Setting interface mode on port 'myproject/layer9_out_2_V' to 'ap_vld'. INFO: [RTGEN 206-500] Setting interface mode on port 'myproject/layer9_out_3_V' to 'ap_vld'. INFO: [RTGEN 206-500] Setting interface mode on port 'myproject/layer9_out_4_V' to 'ap_vld'. INFO: [RTGEN 206-500] Setting interface mode on function 'myproject' to 'ap_ctrl_hs'. INFO: [RTGEN 206-100] Finished creating RTL model for 'myproject'. INFO: [HLS 200-111] Elapsed time: 3.5 seconds; current allocated memory: 1.184 GB. INFO: [HLS 200-789] Estimated Fmax: 250.92 MHz INFO: [RTMG 210-279] Implementing memory 'softmax_stable_ap_fixed_ap_fixed_16_6_5_3_0_softmax_config9_s_exp_table1_rom' using block ROMs. INFO: [RTMG 210-279] Implementing memory 'softmax_stable_ap_fixed_ap_fixed_16_6_5_3_0_softmax_config9_s_invert_table2_rom' using auto ROMs. INFO: [HLS 200-111] Finished generating all RTL models Time (s): cpu = 00:07:23 ; elapsed = 00:07:47 . Memory (MB): peak = 5205.551 ; gain = 4772.445 ; free physical = 2071 ; free virtual = 7091 INFO: [VHDL 208-304] Generating VHDL RTL for myproject. INFO: [VLOG 209-307] Generating Verilog RTL for myproject. **** C/RTL SYNTHESIS COMPLETED IN 0h7m44s INFO: [HLS 200-112] Total elapsed time: 467.13 seconds; peak allocated memory: 1.184 GB. INFO: [Common 17-206] Exiting vivado_hls at Fri Jul 5 17:34:54 2024... Vivado synthesis report not found. Cosim report not found. Timing report not found. Found 1 solution(s) in my-hls-test/myproject_prj. Reports for solution "solution1":
C SIMULATION RESULT: INFO: [SIM 2] CSIM start INFO: [SIM 4] CSIM will launch GCC as the compiler. make: 'csim.exe' is up to date. INFO: Unable to open input/predictions file, using default input. 0.0302734 0.799805 0.0576172 0.147461 0.0390625 INFO: Saved inference results to file: tb_data/csim_results.log INFO: [SIM 1] CSim done with 0 errors. INFO: [SIM 3] CSIM finish
SYNTHESIS REPORT:
== Vivado HLS Report for 'myproject'
Date: Fri Jul 5 17:34:39 2024
Version: 2019.2 (Build 2704478 on Wed Nov 06 22:10:23 MST 2019)
Project: myproject_prj
Solution: solution1
Product family: virtexuplus
Target device: xcvu13p-flga2577-2-e
================================================================ == Performance Estimates
Timing:
Latency:
Summary: +---------+---------+-----------+-----------+-----+-----+----------+ | Latency (cycles) | Latency (absolute) | Interval | Pipeline | | min | max | min | max | min | max | Type | +---------+---------+-----------+-----------+-----+-----+----------+ | 13| 13| 65.000 ns | 65.000 ns | 1| 1| function | +---------+---------+-----------+-----------+-----+-----+----------+
Detail:
Instance: +----------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------+---------+---------+-----------+-----------+-----+-----+----------+ | | | Latency (cycles) | Latency (absolute) | Interval | Pipeline | | Instance | Module | min | max | min | max | min | max | Type | +----------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------+---------+---------+-----------+-----------+-----+-----+----------+ |grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1_fu_97 |dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1 | 1| 1| 5.000 ns | 5.000 ns | 1| 1| function | |grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_fu_165 |dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0 | 1| 1| 5.000 ns | 5.000 ns | 1| 1| function | |grp_dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s_fu_201 |dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s | 1| 1| 5.000 ns | 5.000 ns | 1| 1| function | |grp_dense_latency_ap_fixed_ap_fixed_16_6_5_3_0_config8_0_0_0_0_0_0_fu_207 |dense_latency_ap_fixed_ap_fixed_16_6_5_3_0_config8_0_0_0_0_0_0 | 1| 1| 5.000 ns | 5.000 ns | 1| 1| function | |call_ret1_relu_ap_fixed_16_6_5_3_0_ap_fixed_16_6_5_3_0_relu_config3_s_fu_243 |relu_ap_fixed_16_6_5_3_0_ap_fixed_16_6_5_3_0_relu_config3_s | 0| 0| 0 ns | 0 ns | 1| 1| function | |grp_softmax_stable_ap_fixed_ap_fixed_16_6_5_3_0_softmax_config9_s_fu_311 |softmax_stable_ap_fixed_ap_fixed_16_6_5_3_0_softmax_config9_s | 4| 4| 20.000 ns | 20.000 ns | 1| 1| function | |call_ret3_relu_ap_fixed_16_6_5_3_0_ap_fixed_16_6_5_3_0_relu_config5_s_fu_324 |relu_ap_fixed_16_6_5_3_0_ap_fixed_16_6_5_3_0_relu_config5_s | 0| 0| 0 ns | 0 ns | 1| 1| function | |call_ret5_relu_ap_fixed_16_6_5_3_0_ap_fixed_16_6_5_3_0_relu_config7_s_fu_360 |relu_ap_fixed_16_6_5_3_0_ap_fixed_16_6_5_3_0_relu_config7_s | 0| 0| 0 ns | 0 ns | 1| 1| function | +----------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------+---------+---------+-----------+-----------+-----+-----+----------+
Loop: N/A
================================================================ == Utilization Estimates
Summary: +---------------------+---------+-------+---------+---------+------+ | Name | BRAM_18K| DSP48E| FF | LUT | URAM | +---------------------+---------+-------+---------+---------+------+ |DSP | -| -| -| -| -| |Expression | -| -| 0| 6| -| |FIFO | -| -| -| -| -| |Instance | 4| 3317| 11970| 107013| -| |Memory | -| -| -| -| -| |Multiplexer | -| -| -| 36| -| |Register | -| -| 3424| -| -| +---------------------+---------+-------+---------+---------+------+ |Total | 4| 3317| 15394| 107055| 0| +---------------------+---------+-------+---------+---------+------+ |Available SLR | 1344| 3072| 864000| 432000| 320| +---------------------+---------+-------+---------+---------+------+ |Utilization SLR (%) | ~0 | 107| 1| 24| 0| +---------------------+---------+-------+---------+---------+------+ |Available | 5376| 12288| 3456000| 1728000| 1280| +---------------------+---------+-------+---------+---------+------+ |Utilization (%) | ~0 | 26| ~0 | 6| 0| +---------------------+---------+-------+---------+---------+------+
Detail:
Co-simulation report not found.