fastmachinelearning / hls4ml

Machine learning on FPGAs using HLS
https://fastmachinelearning.org/hls4ml
Apache License 2.0
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IP Core interface #254

Open KOVI89alipes opened 3 years ago

KOVI89alipes commented 3 years ago

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Hi, when you open Vivado HLS project (Vivado 2020, if it matters), you can add port directives. But in the pop-up menu only few possible interfaces are available

https://www.xilinx.com/html_docs/xilinx2017_4/sdaccel_doc/jit1504034365862.html

But why there is no m_axi interface in the list? How does Vivado decide that full axi interface is not applicable here? Is it possible to update HLS project to make m_axi interface available?

Thank you

thesps commented 3 years ago

Hi. Are you using the hls4ml function a the top level of the kernel? You likely need to wrap the hls4ml 'myproject' function in some code to read data from your interface, write into the NN and write back to your interface. You could take this as a starting point: https://github.com/drankincms/hls4ml_c/blob/master/src/aws_hls4ml.cpp