thesps
commented
3 years ago For a CNN model you should set IOType: io_stream in your configuration. Then, if you still see such errors, or the final resources are too large, you should set Strategy: Resource in the HLSConfig section. And finally, try increasing the ReuseFactor.
I can't be sure, but it also looks like you may have ap_fixed<16,6> data types, while you mentioned using QKeras layers in the title. To derive the data types portion of the configuration for a QKeras model, you should generate your config template like:
config = hls4ml.utils.config_from_keras_model(model, granularity='name')
See the 'quantization' part of the hls4ml tutorial for more details, or try it online:
JunningFan
The generated config file with resource strategy is attached:
waldenou
vloncar
Hi,
I'm trying yo use hls4ml to translate a network model with QKeras layers. Sadly, the generated HLS project failed to synthesis in vivado_hls tool. The log, network model, YAML config, and the generated HLS is attached. Any help is appreciated.
model.zip project.zip
Environment: Windows 10 20H2 Vivado and Vivado HLS 2018.2 HLS4ML 0.5.0b0
Log: SyntaxWarning: "is not" with a literal. Did you mean "!="? if found is not 0: 2021-03-02 13:23:17.163205: I tensorflow/stream_executor/platform/default/dso_loader.cc:49] Successfully opened dynamic library cudart64_110.dll Loading configuration from .\my-hls-test/hls4ml_config.yml
** Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2018.2 (64-bit) SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
source D:/Xilinx/Vivado/2018.2/scripts/vivado_hls/hls.tcl -notrace INFO: [HLS 200-10] Running 'D:/Xilinx/Vivado/2018.2/bin/unwrapped/win64.o/vivado_hls.exe' INFO: [HLS 200-10] For user 'haoxi' on host 'haoxi-pc' (Windows NT_amd64 version 6.2) on Tue Mar 02 13:23:20 +1100 2021 INFO: [HLS 200-10] In directory 'E:/DLProjects/hls4ml/my-hls-test' INFO: [HLS 200-10] Creating and opening project 'E:/DLProjects/hls4ml/my-hls-test/myproject_prj'. INFO: [HLS 200-10] Adding design file 'firmware/myproject.cpp' to the project INFO: [HLS 200-10] Adding test bench file 'myproject_test.cpp' to the project INFO: [HLS 200-10] Adding test bench file 'firmware/weights' to the project INFO: [HLS 200-10] Adding test bench file 'tb_data' to the project INFO: [HLS 200-10] Creating and opening solution 'E:/DLProjects/hls4ml/my-hls-test/myproject_prj/solution1'. INFO: [XFORM 203-101] Allowed max sub elements number after partition is 4096. INFO: [XFORM 203-1161] The maximum of name length is set into 60. INFO: [HLS 200-10] Setting target device to 'xc7z020clg484-1' INFO: [SYN 201-201] Setting up clock 'default' with a period of 20ns. INFO: [Common 17-206] Exiting vivado_hls at Tue Mar 2 13:23:20 2021... PS E:\DLProjects\hls4ml> python C:\Users\haoxi\anaconda3\Scripts\hls4ml build -p .\my-hls-test -a C:\Users\haoxi\anaconda3\Scripts\hls4ml:171: SyntaxWarning: "is not" with a literal. Did you mean "!="? if found is not 0: 2021-03-02 13:23:24.678717: I tensorflow/stream_executor/platform/default/dso_loader.cc:49] Successfully opened dynamic library cudart64_110.dll Loading configuration from .\my-hls-test/hls4ml_config.yml
** Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2018.2 (64-bit) SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
source D:/Xilinx/Vivado/2018.2/scripts/vivado_hls/hls.tcl -notrace INFO: [HLS 200-10] Running 'D:/Xilinx/Vivado/2018.2/bin/unwrapped/win64.o/vivado_hls.exe' INFO: [HLS 200-10] For user 'haoxi' on host 'haoxi-pc' (Windows NT_amd64 version 6.2) on Tue Mar 02 13:23:27 +1100 2021 INFO: [HLS 200-10] In directory 'E:/DLProjects/hls4ml/my-hls-test' INFO: [HLS 200-10] Opening project 'E:/DLProjects/hls4ml/my-hls-test/myproject_prj'. INFO: [HLS 200-10] Adding design file 'firmware/myproject.cpp' to the project INFO: [HLS 200-10] Adding test bench file 'myproject_test.cpp' to the project INFO: [HLS 200-10] Adding test bench file 'firmware/weights' to the project INFO: [HLS 200-10] Adding test bench file 'tb_data' to the project INFO: [HLS 200-10] Opening solution 'E:/DLProjects/hls4ml/my-hls-test/myproject_prj/solution1'. INFO: [SYN 201-201] Setting up clock 'default' with a period of 20ns. INFO: [HLS 200-10] Setting target device to 'xc7z020clg484-1' INFO: [XFORM 203-101] Allowed max sub elements number after partition is 4096. INFO: [XFORM 203-1161] The maximum of name length is set into 60. INFO: [XFORM 203-101] Allowed max sub elements number after partition is 4096. INFO: [XFORM 203-1161] The maximum of name length is set into 60. C SIMULATION INFO: [SIM 211-2] CSIM start INFO: [SIM 211-4] CSIM will launch GCC as the compiler. Compiling ../../../../myproject_test.cpp in debug mode Compiling ../../../../firmware/myproject.cpp in debug mode Generating csim.exe In file included from D:/Xilinx/Vivado/2018.2/include/floating_point_v7_0_bitacc_cmodel.h:143:0, from D:/Xilinx/Vivado/2018.2/include/hls_fpo.h:166, from D:/Xilinx/Vivado/2018.2/include/hls_half.h:58, from D:/Xilinx/Vivado/2018.2/include/ap_int_sim.h:73, from D:/Xilinx/Vivado/2018.2/include/ap_int.h:65, from ../../../../firmware/myproject.h:23, from ../../../../myproject_test.cpp:28: D:/Xilinx/Vivado/2018.2/include/gmp.h:62:0: warning: "__GMP_LIBGMP_DLL" redefined
define __GMP_LIBGMP_DLL 0
In file included from D:/Xilinx/Vivado/2018.2/include/hls_fpo.h:166:0, from D:/Xilinx/Vivado/2018.2/include/hls_half.h:58, from D:/Xilinx/Vivado/2018.2/include/ap_int_sim.h:73, from D:/Xilinx/Vivado/2018.2/include/ap_int.h:65, from ../../../../firmware/myproject.h:23, from ../../../../myproject_test.cpp:28: D:/Xilinx/Vivado/2018.2/include/floating_point_v7_0_bitacc_cmodel.h:135:0: note: this is the location of the previous definition
define __GMP_LIBGMP_DLL 1
In file included from D:/Xilinx/Vivado/2018.2/include/floating_point_v7_0_bitacc_cmodel.h:143:0, from D:/Xilinx/Vivado/2018.2/include/hls_fpo.h:166, from D:/Xilinx/Vivado/2018.2/include/hls_half.h:58, from D:/Xilinx/Vivado/2018.2/include/ap_int_sim.h:73, from D:/Xilinx/Vivado/2018.2/include/ap_int.h:65, from ../../../../firmware/myproject.h:23, from ../../../../firmware/myproject.cpp:21: D:/Xilinx/Vivado/2018.2/include/gmp.h:62:0: warning: "__GMP_LIBGMP_DLL" redefined
define __GMP_LIBGMP_DLL 0
In file included from D:/Xilinx/Vivado/2018.2/include/hls_fpo.h:166:0, from D:/Xilinx/Vivado/2018.2/include/hls_half.h:58, from D:/Xilinx/Vivado/2018.2/include/ap_int_sim.h:73, from D:/Xilinx/Vivado/2018.2/include/ap_int.h:65, from ../../../../firmware/myproject.h:23, from ../../../../firmware/myproject.cpp:21: D:/Xilinx/Vivado/2018.2/include/floating_point_v7_0_bitacc_cmodel.h:135:0: note: this is the location of the previous definition
define __GMP_LIBGMP_DLL 1
INFO: Unable to open input/predictions file, using default input. 0.0996094 0.0996094 0.0996094 0.0996094 0.0996094 0.0996094 0.0996094 0.0996094 0.0996094 0.0996094 INFO: Saved inference results to file: tb_data/csim_results.log INFO: [SIM 211-1] CSim done with 0 errors. INFO: [SIM 211-3] CSIM finish C SIMULATION COMPLETED IN 0h0m6s C/RTL SYNTHESIS INFO: [HLS 200-10] Analyzing design file 'firmware/myproject.cpp' ... WARNING: [HLS 200-40] In file included from firmware/myproject.cpp:1: In file included from firmware/myproject.cpp:22: In file included from firmware/parameters.h:13: In file included from firmware/nnet_utils/nnet_conv2d.h:24: firmware/nnet_utils/nnet_conv2d_latency.h:214:69: warning: comparison of unsigned expression < 0 is always false [-Wtautological-compare] if ((oh*CONFIG_T::stride_height+fh) < CONFIG_T::pad_top