Add `zcu104` board to `VivadoAccelerator` backend

[jmduarte]

Add zcu104 board to the VivadoAccelerator backend. Note, it would be nice to add a test that actually generates a bitfile (not just synthesis)

Type of change

• [x] New feature (non-breaking change which adds functionality)

Tests

https://gist.github.com/jmduarte/41a6afcd412dbd7c39cdbd0e2a1a01a3

Checklist

• [x] I have read the guidelines for contributing.
• [x] I have commented my code, particularly in hard-to-understand areas.
• [ ] I have made corresponding changes to the documentation.
• [ ] My changes generate no new warnings.
• [x] I have installed and run pre-commit on the files I edited or added.
• [x] I have added tests that prove my fix is effective or that my feature works.

[jmduarte]

Note I see some warnings when generating the bitfile that may need to be addressed:

WARNING: [xilinx.com:ip:zynq_ultra_ps_e:3.3-1] /zynq_ultra_ps_e_0</axi_smc/M00_AXI> of </axi_smc> is connected to </zynq_ultra_ps_e_0>. To avoid loops, any interface from </zynq_ultra_ps_e_0> should not be connected to </zynq_ultra_ps_e_0> using </axi_smc>
WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /ps8_0_axi_periph/s00_couplers/auto_ds/S_AXI(0) and /zynq_ultra_ps_e_0/M_AXI_HPM0_FPD(16)
WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /ps8_0_axi_periph/s00_couplers/auto_ds/S_AXI(0) and /zynq_ultra_ps_e_0/M_AXI_HPM0_FPD(16)
WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /ps8_0_axi_periph/s01_couplers/auto_ds/S_AXI(0) and /zynq_ultra_ps_e_0/M_AXI_HPM1_FPD(16)
WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /ps8_0_axi_periph/s01_couplers/auto_ds/S_AXI(0) and /zynq_ultra_ps_e_0/M_AXI_HPM1_FPD(16)
WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /zynq_ultra_ps_e_0/S_AXI_HPC0_FPD(1) and /axi_smc/M00_AXI(0)
WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /zynq_ultra_ps_e_0/S_AXI_HPC0_FPD(1) and /axi_smc/M00_AXI(0)
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI_HPM0_FPD'. A default connection has been created.
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI_HPM1_FPD'. A default connection has been created.
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI_HPC0_FPD'. A default connection has been created.
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/users/woodson/issue_740/model_pynq/hls4ml_prj_zcu104/myproject_vivado_accelerator/project_1.srcs/sources_1/bd/design_1/ip/design_1_auto_ds_0/design_1_auto_ds_0_ooc.xdc'
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI'. A default connection has been created.
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI'. A default connection has been created.
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/users/woodson/issue_740/model_pynq/hls4ml_prj_zcu104/myproject_vivado_accelerator/project_1.srcs/sources_1/bd/design_1/ip/design_1_auto_pc_0/design_1_auto_pc_0_ooc.xdc'
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/users/woodson/issue_740/model_pynq/hls4ml_prj_zcu104/myproject_vivado_accelerator/project_1.srcs/sources_1/bd/design_1/ip/design_1_auto_ds_1/design_1_auto_ds_1_ooc.xdc'
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI'. A default connection has been created.
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI'. A default connection has been created.
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/users/woodson/issue_740/model_pynq/hls4ml_prj_zcu104/myproject_vivado_accelerator/project_1.srcs/sources_1/bd/design_1/ip/design_1_auto_pc_1/design_1_auto_pc_1_ooc.xdc'
WARNING: [IP_Flow 19-519] IP 'design_1_myproject_axi_0_0' detected a language mismatch between 'VHDL Simulation Wrapper' and 'Verilog Simulation' output products. Please check with the IP provider to see if this is expected.