fastmachinelearning / hls4ml

Machine learning on FPGAs using HLS
https://fastmachinelearning.org/hls4ml
Apache License 2.0
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SR backend doesn't work with Vitis HLS #994

Open bo3z opened 2 months ago

bo3z commented 2 months ago

Prerequisites

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Quick summary

When synthesising SR with Vitis HLS (2023), co-sim validation fails. The reason for this is that the look-up table constructor, which populates LUT stored in BRAM, is invoked correctly in C++ but not in HLS synthesis, leading to very small/random LUTs that are not sufficient and thus the difference between C++ and HLS simualation.

Possible fix

This is likely an issue in Vitis HLS and not hls4ml. I haven't tested with Vivado HLS as I do not have access to it. Possible fix is to explicitly write-out the LUTs (like it's done with weight arrays), avoiding the need for a constructor.