fatihgulakar
commented
3 months ago Hi,
Converting CA signals from DFI to MIG is pretty straightforward. I didn't finish the adapter because Xilinx MIG PHY requires additional signals for periodic reads, which our memory controller doesn't have. Adding periodic read capability to MC is not difficult. But our company's in-house DDR PHY doesn't need periodic reads, so I have to add it to MC just for Xilinx MIG, which I don't want to.
If you want to test your memory controller on FPGA, I recommend using an Intel FPGA, if possible. Altera FPGAs (Arria 10 for example), have hardened DDR PHY, with an interface called AFI (Altera PHY Interface). AFI has almost the same structure as DFI and does not need periodic reads.
We have tested our memory controller on an Intel FPGA. The MIG adapter is still a TODO, but we have postponed it to a later date.
LOCKEDGATE
Hello, I saw the issue you posted before, as shown below. I have the same problem as you did. My MC only supports DFI, but I want to verify it on xilinx MIG. I have learned some transfer processes before, such as
mc_RAS_n<={6'h3f,{2{dfi_ras_n[0]}}};can transfer dfi_ras_n in DFI protocol to mc_RAS_n of MIG. Therefore, I would like to ask if you have solved this problem?