Build Failed with msx.vhd

[Chandler-Kluser]

When I run build script for altera:

(...)
Info (12021): Found 2 design units, including 1 entities, in source file /workdir/src/peripheral/uart/uart_rx.vhd
    Info (12022): Found design unit 1: uart_rx-rcvr
    Info (12023): Found entity 1: uart_rx
Error (10349): VHDL Association List error at msx.vhd(354): formal "clk" does not exist File: /workdir/src/msx.vhd Line: 354
Error (10346): VHDL error at msx.vhd(352): formal port or parameter "clock_i" must have actual or default value File: /workdir/src/msx.vhd Line: 352
Error (10784): HDL error at ipl_rom.vhd(9): see declaration for object "clock_i" File: /workdir/src/rom/ipl_rom.vhd Line: 9
Error (10346): VHDL error at msx.vhd(352): formal port or parameter "addr_i" must have actual or default value File: /workdir/src/msx.vhd Line: 352
Error (10784): HDL error at ipl_rom.vhd(10): see declaration for object "addr_i" File: /workdir/src/rom/ipl_rom.vhd Line: 10
Info (144001): Generated suppressed messages file /workdir/synth/DE2/output_files/msx_de2.map.smsg
Error: Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 5 errors, 6 warnings
    Error: Peak virtual memory: 615 megabytes
    Error: Processing ended: Sun Dec 24 06:40:33 2023
    Error: Elapsed time: 00:00:01
    Error: Total CPU time (on all processors): 00:00:01
../makefile_altera.inc:45: recipe for target 'output_files/msx_de2.map.rpt' failed
make[1]: *** [output_files/msx_de2.map.rpt] Error 3
make[1]: Leaving directory '/workdir/synth/DE2'
Makefile-altera:12: recipe for target 'synth/DE2' failed
make: *** [synth/DE2] Error 2

and for xilinxise:

(...)
Parsing entity <msx>.
Parsing architecture <Behavior> of entity <msx>.
ERROR:HDLCompiler:1314 - "/workdir/src/msx.vhd" Line 354: Formal port/generic <clk> is not declared in <ipl_rom>
ERROR:HDLCompiler:432 - "/workdir/src/msx.vhd" Line 352: Formal <clock_i> has no actual or default value.
INFO:HDLCompiler:1408 - "/workdir/src/rom/ipl_rom.vhd" Line 9. clock_i is declared here
INFO:HDLCompiler:1408 - "/workdir/src/rom/ipl_rom.vhd" Line 10. addr_i is declared here
ERROR:HDLCompiler:854 - "/workdir/src/msx.vhd" Line 187: Unit <behavior> ignored due to previous errors.
VHDL file /workdir/src/msx.vhd ignored due to errors
--> 

Total memory usage is 315908 kilobytes

Number of errors   :    3 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)

make[1]: *** [../makefile_xilinx.inc:17: qmxc6slx16.ngc] Error 6
make[1]: Leaving directory '/workdir/synth/qmxc6slx16'
make: *** [Makefile-xilinx:11: synth/qmxc6slx16] Error 2

[Chandler-Kluser]

using Quartus II GUI:

[Chandler-Kluser]

The design is synthesizeable in commit e6b149f445ace67e2b1d23019bfcf39eae61e4ca (master branch)