Open majenkotech opened 2 years ago
It could be done, in theory, a couple of ways. SPI to parallel: 8 bit for data and 20 bit for address. Of course 20 bit would be hard to find, so mixing a 16 with an 8 bit one would be true to DOS memory management offset fun. A SPI IO expander could be used for the interrupt signals and the various channel control signals.
The other way, which would be probably faster and easier is with a FPGA programmed to do all of the above. I'm looking to resurrect my senior project from almost 40 years ago, I'm thinking of doing this very thing...
Just as a hypothetical - what would be the feasibility of emulating a real ISA bus on the PC Emulator? Ignore the hardware aspects for now (I'm thinking a bunch of SPI IO expanders like the MCP23S17), but from a software / emulation perspective how realistic do you think it would be to implement it in FabGL? Limited to only the XT's 8 bit bus would be fine.