Open trnila opened 6 years ago
Ok - I am duplicating this problem now. But my stm32f746-disco.dtsi is
{noformat}
/ { reserved-memory {
#size-cells = <1>;
ranges;
linux,dma {
compatible = "shared-dma-pool";
linux,dma-default;
no-map;
reg = <0x20010000 0x3bfff>; /* sram1 240kb */
};
};
clocks {
clk_hse: clk-hse {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
clk-lse {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
};
clk-lsi {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32000>;
};
clk_i2s_ckin: clk-i2s-ckin {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <48000000>;
};
};
soc {
mac: ethernet@40028000 {
compatible = "st,stm32-dwmac", "snps,dwmac-3.50a", "snps,dwmac";
reg = <0x40028000 0x8000>;
reg-names = "stmmaceth";
resets = <&rcc STM32F7_AHB1_RESET(ETHMAC)>;
reset-names = "stmmaceth";
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(ETHMAC)>,
<&rcc 0 STM32F7_AHB1_CLOCK(ETHMACTX)>,
<&rcc 0 STM32F7_AHB1_CLOCK(ETHMACRX)>;
clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
interrupts = <61>, <62>;
interrupt-names = "macirq", "eth_wake_irq";
dma-ranges;
st,syscon = <&syscfg 0x4>;
pinctrl-0 = <ðernet_rmii>;
phy-mode = "rmii";
phy-handle = <&phy0>;
status = "okay";
mdio0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
phy0: ethernet-phy@0 {
reg = <0>;
};
};
};
timer2: timer@40000000 {
compatible = "st,stm32-timer";
reg = <0x40000000 0x400>;
interrupts = <28>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
status = "disabled";
};
timers2: timers@40000000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40000000 0x400>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
clock-names = "int";
status = "disabled";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
};
timer@1 {
compatible = "st,stm32-timer-trigger";
reg = <1>;
status = "disabled";
};
};
timer3: timer@40000400 {
compatible = "st,stm32-timer";
reg = <0x40000400 0x400>;
interrupts = <29>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
status = "disabled";
};
timers3: timers@40000400 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40000400 0x400>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
clock-names = "int";
status = "disabled";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
};
timer@2 {
compatible = "st,stm32-timer-trigger";
reg = <2>;
status = "disabled";
};
};
timer4: timer@40000800 {
compatible = "st,stm32-timer";
reg = <0x40000800 0x400>;
interrupts = <30>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
status = "disabled";
};
timers4: timers@40000800 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40000800 0x400>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
clock-names = "int";
status = "disabled";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
};
timer@3 {
compatible = "st,stm32-timer-trigger";
reg = <3>;
status = "disabled";
};
};
timer5: timer@40000c00 {
compatible = "st,stm32-timer";
reg = <0x40000c00 0x400>;
interrupts = <50>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
};
timers5: timers@40000c00 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40000C00 0x400>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
clock-names = "int";
status = "disabled";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
};
timer@4 {
compatible = "st,stm32-timer-trigger";
reg = <4>;
status = "disabled";
};
};
timer6: timer@40001000 {
compatible = "st,stm32-timer";
reg = <0x40001000 0x400>;
interrupts = <54>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
status = "disabled";
};
timers6: timers@40001000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40001000 0x400>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
clock-names = "int";
status = "disabled";
timer@5 {
compatible = "st,stm32-timer-trigger";
reg = <5>;
status = "disabled";
};
};
timer7: timer@40001400 {
compatible = "st,stm32-timer";
reg = <0x40001400 0x400>;
interrupts = <55>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
status = "disabled";
};
timers7: timers@40001400 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40001400 0x400>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
clock-names = "int";
status = "disabled";
timer@6 {
compatible = "st,stm32-timer-trigger";
reg = <6>;
status = "disabled";
};
};
timers12: timers@40001800 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40001800 0x400>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM12)>;
clock-names = "int";
status = "disabled";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
};
timer@11 {
compatible = "st,stm32-timer-trigger";
reg = <11>;
status = "disabled";
};
};
timers13: timers@40001c00 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40001C00 0x400>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>;
clock-names = "int";
status = "disabled";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
};
};
timers14: timers@40002000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40002000 0x400>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>;
clock-names = "int";
status = "disabled";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
};
};
rtc: rtc@40002800 {
compatible = "st,stm32-rtc";
reg = <0x40002800 0x400>;
clocks = <&rcc 1 CLK_RTC>;
clock-names = "ck_rtc";
assigned-clocks = <&rcc 1 CLK_RTC>;
assigned-clock-parents = <&rcc 1 CLK_LSE>;
interrupt-parent = <&exti>;
interrupts = <17 1>;
interrupt-names = "alarm";
st,syscfg = <&pwrcfg>;
status = "disabled";
};
usart2: serial@40004400 {
compatible = "st,stm32f7-uart";
reg = <0x40004400 0x400>;
interrupts = <38>;
clocks = <&rcc 1 CLK_USART2>;
status = "disabled";
};
usart3: serial@40004800 {
compatible = "st,stm32f7-uart";
reg = <0x40004800 0x400>;
interrupts = <39>;
clocks = <&rcc 1 CLK_USART3>;
status = "disabled";
};
usart4: serial@40004c00 {
compatible = "st,stm32f7-uart";
reg = <0x40004c00 0x400>;
interrupts = <52>;
clocks = <&rcc 1 CLK_UART4>;
status = "disabled";
};
usart5: serial@40005000 {
compatible = "st,stm32f7-uart";
reg = <0x40005000 0x400>;
interrupts = <53>;
clocks = <&rcc 1 CLK_UART5>;
status = "disabled";
};
i2c1: i2c@40005400 {
compatible = "st,stm32f7-i2c";
reg = <0x40005400 0x400>;
interrupts = <31>,
<32>;
resets = <&rcc STM32F7_APB1_RESET(I2C1)>;
clocks = <&rcc 1 CLK_I2C1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
cec: cec@40006c00 {
compatible = "st,stm32-cec";
reg = <0x40006C00 0x400>;
interrupts = <94>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(CEC)>, <&rcc 1 CLK_HDMI_CEC>;
clock-names = "cec", "hdmi-cec";
status = "disabled";
};
usart7: serial@40007800 {
compatible = "st,stm32f7-uart";
reg = <0x40007800 0x400>;
interrupts = <82>;
clocks = <&rcc 1 CLK_UART7>;
status = "disabled";
};
usart8: serial@40007c00 {
compatible = "st,stm32f7-uart";
reg = <0x40007c00 0x400>;
interrupts = <83>;
clocks = <&rcc 1 CLK_UART8>;
status = "disabled";
};
timers1: timers@40010000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40010000 0x400>;
clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM1)>;
clock-names = "int";
status = "disabled";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
};
timer@0 {
compatible = "st,stm32-timer-trigger";
reg = <0>;
status = "disabled";
};
};
timers8: timers@40010400 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40010400 0x400>;
clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM8)>;
clock-names = "int";
status = "disabled";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
};
timer@7 {
compatible = "st,stm32-timer-trigger";
reg = <7>;
status = "disabled";
};
};
usart1: serial@40011000 {
compatible = "st,stm32f7-uart";
reg = <0x40011000 0x400>;
interrupts = <37>;
clocks = <&rcc 1 CLK_USART1>;
status = "disabled";
};
usart6: serial@40011400 {
compatible = "st,stm32f7-uart";
reg = <0x40011400 0x400>;
interrupts = <71>;
clocks = <&rcc 1 CLK_USART6>;
status = "disabled";
};
syscfg: system-config@40013800 {
compatible = "syscon";
reg = <0x40013800 0x400>;
};
exti: interrupt-controller@40013c00 {
compatible = "st,stm32-exti";
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x40013C00 0x400>;
interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
};
timers9: timers@40014000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40014000 0x400>;
clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM9)>;
clock-names = "int";
status = "disabled";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
};
timer@8 {
compatible = "st,stm32-timer-trigger";
reg = <8>;
status = "disabled";
};
};
timers10: timers@40014400 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40014400 0x400>;
clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM10)>;
clock-names = "int";
status = "disabled";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
};
};
timers11: timers@40014800 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40014800 0x400>;
clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM11)>;
clock-names = "int";
status = "disabled";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
};
};
pwrcfg: power-config@40007000 {
compatible = "syscon";
reg = <0x40007000 0x400>;
};
pin-controller {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,stm32f746-pinctrl";
ranges = <0 0x40020000 0x3000>;
interrupt-parent = <&exti>;
st,syscfg = <&syscfg 0x8>;
pins-are-numbered;
gpioa: gpio@40020000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x0 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>;
st,bank-name = "GPIOA";
};
gpiob: gpio@40020400 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x400 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>;
st,bank-name = "GPIOB";
};
gpioc: gpio@40020800 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x800 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>;
st,bank-name = "GPIOC";
};
gpiod: gpio@40020c00 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0xc00 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>;
st,bank-name = "GPIOD";
};
gpioe: gpio@40021000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x1000 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>;
st,bank-name = "GPIOE";
};
gpiof: gpio@40021400 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x1400 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>;
st,bank-name = "GPIOF";
};
gpiog: gpio@40021800 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x1800 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>;
st,bank-name = "GPIOG";
};
gpioh: gpio@40021c00 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x1c00 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>;
st,bank-name = "GPIOH";
};
gpioi: gpio@40022000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x2000 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>;
st,bank-name = "GPIOI";
};
gpioj: gpio@40022400 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x2400 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOJ)>;
st,bank-name = "GPIOJ";
};
gpiok: gpio@40022800 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x2800 0x400>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOK)>;
st,bank-name = "GPIOK";
};
cec_pins_a: cec@0 {
pins {
pinmux = <STM32_PINMUX('A', 15, AF4)>; /* HDMI CEC */
slew-rate = <0>;
drive-open-drain;
bias-disable;
};
};
usart1_pins_a: usart1@0 {
pins1 {
pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('A', 10, AF7)>; /* USART1_RX */
bias-disable;
};
};
usart1_pins_b: usart1@1 {
pins1 {
pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('B', 7, AF7)>; /* USART1_RX */
bias-disable;
};
};
i2c1_pins_b: i2c1@0 {
pins {
pinmux = <STM32_PINMUX('B', 9, AF4)>, /* I2C1 SDA */
<STM32_PINMUX('B', 8, AF4)>; /* I2C1 SCL */
bias-disable;
drive-open-drain;
slew-rate = <0>;
};
};
usbotg_hs_pins_a: usbotg-hs@0 {
pins {
pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT */
<STM32_PINMUX('I', 11, AF10)>, /* OTG_HS_ULPI_DIR */
<STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */
<STM32_PINMUX('A', 5, AF10)>, /* OTG_HS_ULPI_CK */
<STM32_PINMUX('A', 3, AF10)>, /* OTG_HS_ULPI_D0 */
<STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */
<STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */
<STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */
<STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */
<STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */
<STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */
<STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */
bias-disable;
drive-push-pull;
slew-rate = <2>;
};
};
usbotg_hs_pins_b: usbotg-hs@1 {
pins {
pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT */
<STM32_PINMUX('C', 2, AF10)>, /* OTG_HS_ULPI_DIR */
<STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */
<STM32_PINMUX('A', 5, AF10)>, /* OTG_HS_ULPI_CK */
<STM32_PINMUX('A', 3, AF10)>, /* OTG_HS_ULPI_D0 */
<STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */
<STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */
<STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */
<STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */
<STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */
<STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */
<STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */
bias-disable;
drive-push-pull;
slew-rate = <2>;
};
};
usbotg_fs_pins_a: usbotg-fs@0 {
pins {
pinmux = <STM32_PINMUX('A', 10, AF10)>, /* OTG_FS_ID */
<STM32_PINMUX('A', 11, AF10)>, /* OTG_FS_DM */
<STM32_PINMUX('A', 12, AF10)>; /* OTG_FS_DP */
bias-disable;
drive-push-pull;
slew-rate = <2>;
};
};
ethernet_rmii: rmii@0 {
pins {
pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH_RMII_TXD0 */
<STM32_PINMUX('G', 14, AF11)>, /* ETH_RMII_TXD1 */
<STM32_PINMUX('G', 11, AF11)>, /* ETH_RMII_TX_EN */
<STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */
<STM32_PINMUX('C', 1, AF11)>, /* ETH_MDC */
<STM32_PINMUX('A', 1, AF11)>, /* ETH_RMII_REF_CLK */
<STM32_PINMUX('A', 7, AF11)>, /* ETH_RMII_CRS_DV */
<STM32_PINMUX('C', 4, AF11)>, /* ETH_RMII_RXD0 */
<STM32_PINMUX('C', 5, AF11)>; /* ETH_RMII_RXD1 */
/*
pinmux =
making some progress here
~ # ifconfig eth0 up 192.168.1.250
[ 11.365572] stm32-dwmac 40028000.ethernet eth0: device MAC address 92:27:a9:78:7e:e1
[ 11.376138] Generic PHY stmmac-0:00: attached PHY driver [Generic PHY] (mii_bus:phy_addr=stmmac-0:00, irq=POLL)
[ 11.407535] stm32-dwmac 40028000.ethernet eth0: No Safety Features support found
[ 11.415266] stm32-dwmac 40028000.ethernet eth0: IEEE 1588-2008 Advanced Timestamp supported
[ 11.426347] stm32-dwmac 40028000.ethernet eth0: registered PTP clock
[ 11.434405] stmmac: (ptrval) <= 0041848c ETH_MACCR
[ 11.439460] stmmac: (ptrval) <= 00000010 ETH_MACMIIAR
[ 11.444527] stmmac: (ptrval) <= 00003100 ETH_MACMIIDR
[ 11.449848] stmmac: (ptrval) <= 00000200 ETH_MACIMR
[ 11.454745] stmmac: (ptrval) <= 8000e17e ETH_MACA0HR
[ 11.459976] stmmac: (ptrval) <= 78a92792 ETH_MACA0LR
[ 11.464950] stmmac: (ptrval) <= 00000024 ETH_MMCCR
[ 11.470008] stmmac: (ptrval) <= 00ffffff ETH_MMCRIMR
[ 11.474987] stmmac: (ptrval) <= 01ffffff ETH_MMCTIMR
[ 11.480229] stmmac: (ptrval) <= 20010000 ETH_DMARDLAR
[ 11.485294] stmmac: (ptrval) <= 20014000 ETH_DMATDLAR
[ 11.490616] stmmac: (ptrval) <= 02202006 ETH_DMAOMR
[ 11.495507] stmmac: (ptrval) <= 0001a061 ETH_DMAIER
[ 11.503339] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
~ # [ 12.491707] stm32-dwmac 40028000.ethernet eth0: Link is Up - 100Mbps/Full - flow control rx/tx
[ 12.500698] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
[ 18.409153] ------------[ cut here ]------------
[ 18.413906] WARNING: CPU: 0 PID: 0 at net/sched/sch_generic.c:461 dev_watchdog+0xfd/0x19c
[ 18.422102] NETDEV WATCHDOG: eth0 (stm32-dwmac): transmit queue 0 timed out
[ 18.429135] CPU: 0 PID: 0 Comm: swapper Not tainted 4.19.0 #33
[ 18.434961] Hardware name: STM32 (Device Tree Support)
[ 18.440295] [<c000c0c9>] (unwind_backtrace) from [<c000b223>] (show_stack+0xb/0xc)
[ 18.448044] [<c000b223>] (show_stack) from [<c000eb0f>] (__warn+0x87/0xa0)
[ 18.455093] [<c000eb0f>] (__warn) from [<c000eb4f>] (warn_slowpath_fmt+0x27/0x40)
[ 18.462773] [<c000eb4f>] (warn_slowpath_fmt) from [<c01a450d>] (dev_watchdog+0xfd/0x19c)
[ 18.471064] [<c01a450d>] (dev_watchdog) from [<c0037b49>] (call_timer_fn+0xf/0x56)
[ 18.478821] [<c0037b49>] (call_timer_fn) from [<c0037ccb>] (expire_timers+0x7b/0x7e)
[ 18.486758] [<c0037ccb>] (expire_timers) from [<c0037ecd>] (run_timer_softirq+0xf5/0x140)
[ 18.495125] [<c0037ecd>] (run_timer_softirq) from [<c000994d>] (__do_softirq+0xf5/0x14c)
[ 18.503402] [<c000994d>] (__do_softirq) from [<c001098d>] (irq_exit+0x3d/0x80)
[ 18.510812] [<c001098d>] (irq_exit) from [<c002be75>] (__handle_domain_irq+0x47/0x6a)
[ 18.518830] [<c002be75>] (__handle_domain_irq) from [<c000ba83>] (__irq_entry+0x53/0x84)
[ 18.526947] ---[ end trace 0eb52e36aeb5afb5 ]---
This patch works for me stm32f746-disco-get-ethernet-working.diff.gz
pretty version is linked here on GitHub
Note: DMA is not working on the i2c or uart devices. Probably more devicetree entries needed.
$ ping -c 100 192.168.1.250
PING 192.168.1.250 (192.168.1.250) 56(84) bytes of data.
64 bytes from 192.168.1.250: icmp_seq=1 ttl=64 time=6.61 ms
...
64 bytes from 192.168.1.250: icmp_seq=100 ttl=64 time=4.92 ms
--- 192.168.1.250 ping statistics ---
100 packets transmitted, 100 received, 0% packet loss, time 99162ms
rtt min/avg/max/mdev = 1.710/4.397/10.945/1.265 ms
Also, because you did not mention this way of configuring kernel to set up Ethernet in this thread, so I made the settings myself in the kernel, which, of course, do not know if it is enough or not.
Strange.
After applying these patches, I rebuilt my kernel with
make ARCH=arm CROSS_COMPILE=arm-none-eabi- stm32_defconfig
make ARCH=arm CROSS_COMPILE=arm-none-eabi-
and have not had any issues (although dma still does not work with uart / i2c)
You have console access on ttySTM0, right?
Sorry - my bad - I should have clarified that the STM32 will boot linux and use ttySTM0 as the console.
My exact config is here.
Other than that, everything else should be in the branch
Note, the part that says
I've noticed that U-Boot bootargs trump these
* I suggest adding the following to your U-Boot .config
* CONFIG_BOOTARGS="console=ttySTM0,115200n8"
Can somebody help me step by step to enable ethernet for this board?
I was able to overcome this problem with the following patch:
drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
index 9e6db16af..63d6f388b 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
@@ -22,7 +22,9 @@
#include "stmmac_platform.h"
-#define MII_PHY_SEL_MASK BIT(23)
+#define STM32_SYSCFG_PMC_ETHMODE_MASK (0x3 << 23)
+#define STM32_SYSCFG_PMC_ETHMODE_MII (0x0 << 23)
+#define STM32_SYSCFG_PMC_ETHMODE_RMII (0x1 << 23)
struct stm32_dwmac {
struct clk *clk_tx;
@@ -39,8 +41,8 @@ static int stm32_dwmac_init(struct plat_stmmacenet_data *plat_dat)
u32 val;
int ret;
- val = (plat_dat->interface == PHY_INTERFACE_MODE_MII) ? 0 : 1;
- ret = regmap_update_bits(dwmac->regmap, reg, MII_PHY_SEL_MASK, val);
+ val = (plat_dat->interface == PHY_INTERFACE_MODE_MII) ? STM32_SYSCFG_PMC_ETHMODE_MII : STM32_SYSCFG_PMC_ETHMODE_RMII;
+ ret = regmap_update_bits(dwmac->regmap, reg, STM32_SYSCFG_PMC_ETHMODE_MASK, val);
if (ret)
return ret;
--
Hi, I applied both patches, @cfriedt and @rodrigo455, with the configuration of @cfriedt , and got stuck in the following part in both of them:
_~ # ifconfig eth0 up 192.168.0.123
[ 50.320000] stm32-dwmac 40028000.ethernet eth0: device MAC address b2:09:eb:cc:42:88
[ 50.530000] Generic PHY stmmac-0:00: attached PHY driver [Generic PHY] (mii_bus:phy_addr=stmmac-0:00, irq=POLL)
[ 50.550000] stm32-dwmac 40028000.ethernet eth0: IEEE 1588-2008 Advanced Timestamp supported
[ 50.560000] stm32-dwmac 40028000.ethernet eth0: registered PTP clock
[ 50.560000] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
~ # [ 52.010000] stm32-dwmac 40028000.ethernet eth0: Link is Up - 100Mbps/Full - flow control off
[ 52.010000] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
[ 57.440000] ------------[ cut here ]------------
[ 57.440000] WARNING: CPU: 0 PID: 0 at net/sched/sch_generic.c:323 dev_watchdog+0xfd/0x19c
[ 57.440000] NETDEV WATCHDOG: eth0 (stm32-dwmac): transmit queue 0 timed out
[ 57.440000] CPU: 0 PID: 0 Comm: swapper Not tainted 4.15.7 #2
[ 57.440000] Hardware name: STM32 (Device Tree Support)
[ 57.440000] [
if after this if I try ifconfig or ping I get the following error output:
~ # ifconfig
[ 199.390000] ifconfig: page allocation failure: order:7, mode:0x14000c0(GFP_KERNEL), nodemask=(null)
[ 199.390000] CPU: 0 PID: 57 Comm: ifconfig Tainted: G W 4.15.7 #2
[ 199.390000] Hardware name: STM32 (Device Tree Support)
[ 199.390000] [
Does anyone have a hint on why am I getting this error applying the exact same configuration and patches?
Thanks in advance
It looks like the defines added in the above patch ate likely bogus. They define those symbols to nothing..
Thanks for the fast reply @cfriedt , I'm not sure I understood what yo mean, since I took the exact same configuration and version as yours and used your patch, I don't know what I may have done wrong in the process, do you have any hint about it or any possible solution? Thanks
Thanks for the fast reply @cfriedt , I'm not sure I understood what yo mean, since I took the exact same configuration and version as yours and used your patch, I don't know what I may have done wrong in the process, do you have any hint about it or any possible solution? Thanks
There is a patch listed above that someone claimed resolved their DMA issue. It is not mine. That's what I was referring to.
In terms of what you've done wrong, I have no idea. It's possible that source code has evolved since then. My comments applied to things 4 years ago but might be out of date now.
You may need to debug the issue yourself.
Hello, I am trying to get ethernet working, but I have some issue with the following device tree configuration.
When I try to bring ethernet up, it fails on resetting ethernet's dma (https://github.com/torvalds/linux/blob/b9849860675f925da0380f4ea76c3f5041909737/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c#L35). Bit 0 SR of register ETH_DMABMR is never cleared, so reset haven't completed (even when I increased timeout slightly).
Do you see any problem? Thank you