Add support for RISC-V architecture

[yeongjoshua]

Tested on VisionFive 2 Board. The cpuinfo would look like this. Adding this will add support to RISC-V chips.

[fenrus75]

this patch looks good.. is there a problem with it for you to close this?

[yeongjoshua]

I saw a note where I need to submit patch through mailing list, which I still fail to understand how it works

[renat-sabitov]

It's a little bit different for T-Head 1520 CPU (Lichee Pi 4A). I suggest using isa line to mark the end of processing.

sipeed@lpi4a:~$ cat /proc/cpuinfo 
processor   : 0
hart        : 0
isa     : rv64imafdcvsu
mmu     : sv39
cpu-freq    : 1.848Ghz
cpu-icache  : 64KB
cpu-dcache  : 64KB
cpu-l2cache : 1MB
cpu-tlb     : 1024 4-ways
cpu-cacheline   : 64Bytes
cpu-vector  : 0.7.1

processor   : 1
hart        : 1
isa     : rv64imafdcvsu
mmu     : sv39
cpu-freq    : 1.848Ghz
cpu-icache  : 64KB
cpu-dcache  : 64KB
cpu-l2cache : 1MB
cpu-tlb     : 1024 4-ways
cpu-cacheline   : 64Bytes
cpu-vector  : 0.7.1

processor   : 2
hart        : 2
isa     : rv64imafdcvsu
mmu     : sv39
cpu-freq    : 1.848Ghz
cpu-icache  : 64KB
cpu-dcache  : 64KB
cpu-l2cache : 1MB
cpu-tlb     : 1024 4-ways
cpu-cacheline   : 64Bytes
cpu-vector  : 0.7.1

processor   : 3
hart        : 3
isa     : rv64imafdcvsu
mmu     : sv39
cpu-freq    : 1.848Ghz
cpu-icache  : 64KB
cpu-dcache  : 64KB
cpu-l2cache : 1MB
cpu-tlb     : 1024 4-ways
cpu-cacheline   : 64Bytes
cpu-vector  : 0.7.1